Fixes to get compiling to work. This is mainly fixing up some includes; changing functions within the XCs; changing MemReqPtrs to Requests or Packets where appropriate.
Currently the O3 and Ozone CPUs do not work in the new memory system; I still need to fix up the ports to work and handle responses properly. This check-in is so that the merge between m5 and newmem is no longer outstanding.
src/SConscript:
Need to include FU Pool for new CPU model. I'll try to figure out a cleaner way to handle this in the future.
src/base/traceflags.py:
Include new traces flags, fix up merge mess up.
src/cpu/SConscript:
Include the base_dyn_inst.cc as one of othe sources.
Don't compile the Ozone CPU for now.
src/cpu/base.cc:
Remove an extra } from the merge.
src/cpu/base_dyn_inst.cc:
Fixes to make compiling work. Don't instantiate the OzoneCPU for now.
src/cpu/base_dyn_inst.hh:
src/cpu/o3/2bit_local_pred.cc:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/btb.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/free_list.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/sat_counter.hh:
src/cpu/op_class.hh:
src/cpu/ozone/cpu.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/checker/o3_cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/mem/request.hh:
src/cpu/o3/fu_pool.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/dyn_inst.cc:
src/cpu/ozone/dyn_inst.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/ozone_impl.hh:
src/cpu/ozone/thread_state.hh:
Fixes to get compiling to work.
src/cpu/o3/alpha_cpu.hh:
Fixes to get compiling to work.
Float reg accessors have changed, as well as MemReqPtrs to RequestPtrs.
src/cpu/o3/alpha_dyn_inst_impl.hh:
Fixes to get compiling to work.
Pass in the packet to the completeAcc function.
Fix up syscall function.
--HG--
rename : cpu/activity.cc => src/cpu/activity.cc
rename : cpu/activity.hh => src/cpu/activity.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu.cc
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/checker/cpu_builder.cc
rename : cpu/checker/exec_context.hh => src/cpu/checker/exec_context.hh
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_cpu_builder.cc
rename : cpu/o3/dep_graph.hh => src/cpu/o3/dep_graph.hh
rename : cpu/o3/fu_pool.cc => src/cpu/o3/fu_pool.cc
rename : cpu/o3/fu_pool.hh => src/cpu/o3/fu_pool.hh
rename : cpu/o3/lsq.cc => src/cpu/o3/lsq.cc
rename : cpu/o3/lsq.hh => src/cpu/o3/lsq.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.cc => src/cpu/o3/lsq_unit.cc
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/scoreboard.cc => src/cpu/o3/scoreboard.cc
rename : cpu/o3/scoreboard.hh => src/cpu/o3/scoreboard.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/ozone/back_end.cc => src/cpu/ozone/back_end.cc
rename : cpu/ozone/back_end.hh => src/cpu/ozone/back_end.hh
rename : cpu/ozone/back_end_impl.hh => src/cpu/ozone/back_end_impl.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/dyn_inst.cc => src/cpu/ozone/dyn_inst.cc
rename : cpu/ozone/dyn_inst.hh => src/cpu/ozone/dyn_inst.hh
rename : cpu/ozone/dyn_inst_impl.hh => src/cpu/ozone/dyn_inst_impl.hh
rename : cpu/ozone/front_end.cc => src/cpu/ozone/front_end.cc
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end.cc => src/cpu/ozone/inorder_back_end.cc
rename : cpu/ozone/inorder_back_end.hh => src/cpu/ozone/inorder_back_end.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue.cc => src/cpu/ozone/inst_queue.cc
rename : cpu/ozone/inst_queue.hh => src/cpu/ozone/inst_queue.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lsq_unit.cc => src/cpu/ozone/lsq_unit.cc
rename : cpu/ozone/lsq_unit.hh => src/cpu/ozone/lsq_unit.hh
rename : cpu/ozone/lsq_unit_impl.hh => src/cpu/ozone/lsq_unit_impl.hh
rename : cpu/ozone/lw_back_end.cc => src/cpu/ozone/lw_back_end.cc
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.cc => src/cpu/ozone/lw_lsq.cc
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/null_predictor.hh => src/cpu/ozone/null_predictor.hh
rename : cpu/ozone/ozone_impl.hh => src/cpu/ozone/ozone_impl.hh
rename : cpu/ozone/rename_table.cc => src/cpu/ozone/rename_table.cc
rename : cpu/ozone/rename_table.hh => src/cpu/ozone/rename_table.hh
rename : cpu/ozone/rename_table_impl.hh => src/cpu/ozone/rename_table_impl.hh
rename : cpu/ozone/simple_impl.hh => src/cpu/ozone/simple_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/quiesce_event.cc => src/cpu/quiesce_event.cc
rename : cpu/quiesce_event.hh => src/cpu/quiesce_event.hh
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : python/m5/objects/FUPool.py => src/python/m5/objects/FUPool.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/SimpleOzoneCPU.py => src/python/m5/objects/SimpleOzoneCPU.py
extra : convert_revision : ca7f0fbf65ee1a70d482fb4eda9a1840c7f9b8f8
This commit is contained in:
Kevin Lim
8
src/python/m5/objects/FUPool.py
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8
src/python/m5/objects/FUPool.py
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from m5 import *
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from FullCPU import OpType
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from FullCPU import OpDesc
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from FullCPU import FUDesc
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class FUPool(SimObject):
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type = 'FUPool'
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FUList = VectorParam.FUDesc("list of FU's for this pool")
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89
src/python/m5/objects/OzoneCPU.py
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89
src/python/m5/objects/OzoneCPU.py
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from m5 import *
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from BaseCPU import BaseCPU
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class DerivOzoneCPU(BaseCPU):
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type = 'DerivOzoneCPU'
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numThreads = Param.Unsigned("number of HW thread contexts")
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if not build_env['FULL_SYSTEM']:
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mem = Param.FunctionalMemory(NULL, "memory")
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checker = Param.BaseCPU("Checker CPU")
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width = Param.Unsigned("Width")
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frontEndWidth = Param.Unsigned("Front end width")
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backEndWidth = Param.Unsigned("Back end width")
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backEndSquashLatency = Param.Unsigned("Back end squash latency")
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backEndLatency = Param.Unsigned("Back end latency")
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maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
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maxOutstandingMemOps = Param.Unsigned("Maximum number of outstanding memory operations")
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decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
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renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
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iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
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"delay")
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commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
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fetchWidth = Param.Unsigned("Fetch width")
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renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
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iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
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"delay")
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commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
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fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
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decodeWidth = Param.Unsigned("Decode width")
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iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
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"delay")
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commitToRenameDelay = Param.Unsigned("Commit to rename delay")
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decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
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renameWidth = Param.Unsigned("Rename width")
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commitToIEWDelay = Param.Unsigned("Commit to "
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"Issue/Execute/Writeback delay")
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renameToIEWDelay = Param.Unsigned("Rename to "
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"Issue/Execute/Writeback delay")
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issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
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"to the IEW stage)")
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issueWidth = Param.Unsigned("Issue width")
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executeWidth = Param.Unsigned("Execute width")
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executeIntWidth = Param.Unsigned("Integer execute width")
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executeFloatWidth = Param.Unsigned("Floating point execute width")
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executeBranchWidth = Param.Unsigned("Branch execute width")
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executeMemoryWidth = Param.Unsigned("Memory execute width")
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iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
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"delay")
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renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
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commitWidth = Param.Unsigned("Commit width")
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squashWidth = Param.Unsigned("Squash width")
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localPredictorSize = Param.Unsigned("Size of local predictor")
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localCtrBits = Param.Unsigned("Bits per counter")
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localHistoryTableSize = Param.Unsigned("Size of local history table")
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localHistoryBits = Param.Unsigned("Bits for the local history")
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globalPredictorSize = Param.Unsigned("Size of global predictor")
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globalCtrBits = Param.Unsigned("Bits per counter")
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globalHistoryBits = Param.Unsigned("Bits of history")
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choicePredictorSize = Param.Unsigned("Size of choice predictor")
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choiceCtrBits = Param.Unsigned("Bits of choice counters")
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BTBEntries = Param.Unsigned("Number of BTB entries")
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BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
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RASSize = Param.Unsigned("RAS size")
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LQEntries = Param.Unsigned("Number of load queue entries")
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SQEntries = Param.Unsigned("Number of store queue entries")
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LFSTSize = Param.Unsigned("Last fetched store table size")
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SSITSize = Param.Unsigned("Store set ID table size")
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numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
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numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
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"registers")
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numIQEntries = Param.Unsigned("Number of instruction queue entries")
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numROBEntries = Param.Unsigned("Number of reorder buffer entries")
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instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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86
src/python/m5/objects/SimpleOzoneCPU.py
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86
src/python/m5/objects/SimpleOzoneCPU.py
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@@ -0,0 +1,86 @@
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from m5 import *
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from BaseCPU import BaseCPU
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class SimpleOzoneCPU(BaseCPU):
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type = 'SimpleOzoneCPU'
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numThreads = Param.Unsigned("number of HW thread contexts")
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if not build_env['FULL_SYSTEM']:
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mem = Param.FunctionalMemory(NULL, "memory")
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width = Param.Unsigned("Width")
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frontEndWidth = Param.Unsigned("Front end width")
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backEndWidth = Param.Unsigned("Back end width")
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backEndSquashLatency = Param.Unsigned("Back end squash latency")
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backEndLatency = Param.Unsigned("Back end latency")
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maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
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decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
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renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
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iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
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"delay")
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commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
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fetchWidth = Param.Unsigned("Fetch width")
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renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
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iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
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"delay")
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commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
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fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
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decodeWidth = Param.Unsigned("Decode width")
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iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
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"delay")
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commitToRenameDelay = Param.Unsigned("Commit to rename delay")
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decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
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renameWidth = Param.Unsigned("Rename width")
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commitToIEWDelay = Param.Unsigned("Commit to "
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"Issue/Execute/Writeback delay")
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renameToIEWDelay = Param.Unsigned("Rename to "
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"Issue/Execute/Writeback delay")
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issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
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"to the IEW stage)")
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issueWidth = Param.Unsigned("Issue width")
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executeWidth = Param.Unsigned("Execute width")
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executeIntWidth = Param.Unsigned("Integer execute width")
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executeFloatWidth = Param.Unsigned("Floating point execute width")
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executeBranchWidth = Param.Unsigned("Branch execute width")
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executeMemoryWidth = Param.Unsigned("Memory execute width")
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iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
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"delay")
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renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
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commitWidth = Param.Unsigned("Commit width")
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squashWidth = Param.Unsigned("Squash width")
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localPredictorSize = Param.Unsigned("Size of local predictor")
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localCtrBits = Param.Unsigned("Bits per counter")
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localHistoryTableSize = Param.Unsigned("Size of local history table")
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localHistoryBits = Param.Unsigned("Bits for the local history")
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globalPredictorSize = Param.Unsigned("Size of global predictor")
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globalCtrBits = Param.Unsigned("Bits per counter")
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globalHistoryBits = Param.Unsigned("Bits of history")
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choicePredictorSize = Param.Unsigned("Size of choice predictor")
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choiceCtrBits = Param.Unsigned("Bits of choice counters")
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BTBEntries = Param.Unsigned("Number of BTB entries")
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BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
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RASSize = Param.Unsigned("RAS size")
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LQEntries = Param.Unsigned("Number of load queue entries")
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SQEntries = Param.Unsigned("Number of store queue entries")
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LFSTSize = Param.Unsigned("Last fetched store table size")
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SSITSize = Param.Unsigned("Store set ID table size")
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numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
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numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
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"registers")
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numIQEntries = Param.Unsigned("Number of instruction queue entries")
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numROBEntries = Param.Unsigned("Number of reorder buffer entries")
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instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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