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Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp"

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--HG--
extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
This commit is contained in:
Korey Sewell
2007-11-15 03:10:41 -05:00
parent 375ddf8d25
commit 789153dff6
10 changed files with 52 additions and 69 deletions
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5
src/cpu/o3/thread_context.hh
View File

@@ -117,13 +117,13 @@ class O3ThreadContext : public ThreadContext
virtual void activate(int delay = 1);
/** Set the status to Suspended. */
virtual void suspend();
virtual void suspend(int delay = 0);
/** Set the status to Unallocated. */
virtual void deallocate(int delay = 0);
/** Set the status to Halted. */
virtual void halt();
virtual void halt(int delay = 0);
#if FULL_SYSTEM
/** Dumps the function profiling information.
@@ -236,7 +236,6 @@ class O3ThreadContext : public ThreadContext
* misspeculating, this is set as false. */
virtual bool misspeculating() { return false; }
virtual void setShadowSet(int ss) { };
#if !FULL_SYSTEM
/** Gets a syscall argument by index. */
virtual IntReg getSyscallArg(int i);

42
src/cpu/o3/thread_context_impl.hh
View File

@@ -136,7 +136,7 @@ O3ThreadContext<Impl>::activate(int delay)
template <class Impl>
void
O3ThreadContext<Impl>::suspend()
O3ThreadContext<Impl>::suspend(int delay)
{
DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
getThreadNum());
@@ -177,7 +177,7 @@ O3ThreadContext<Impl>::deallocate(int delay)
template <class Impl>
void
O3ThreadContext<Impl>::halt()
O3ThreadContext<Impl>::halt(int delay)
{
DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
getThreadNum());
@@ -289,13 +289,9 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
// Copy the misc regs.
TheISA::copyMiscRegs(tc, this);
// Then finally set the PC, the next PC, the nextNPC, the micropc, and the
// next micropc.
// Then finally set the PC and the next PC.
cpu->setPC(tc->readPC(), tid);
cpu->setNextPC(tc->readNextPC(), tid);
cpu->setNextNPC(tc->readNextNPC(), tid);
cpu->setMicroPC(tc->readMicroPC(), tid);
cpu->setNextMicroPC(tc->readNextMicroPC(), tid);
#if !FULL_SYSTEM
this->thread->funcExeInst = tc->readFuncExeInst();
#endif
@@ -318,7 +314,6 @@ template <class Impl>
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
{
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
switch(width) {
case 32:
return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
@@ -334,7 +329,6 @@ template <class Impl>
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx)
{
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
}
@@ -343,7 +337,6 @@ TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
{
DPRINTF(Fault, "Reading floatint register through the TC!\n");
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
}
@@ -351,7 +344,6 @@ template <class Impl>
TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
{
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
}
@@ -372,7 +364,6 @@ template <class Impl>
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
{
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
switch(width) {
case 32:
cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
@@ -392,7 +383,6 @@ template <class Impl>
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
if (!thread->trapPending && !thread->inSyscall) {
@@ -406,7 +396,6 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
int width)
{
DPRINTF(Fault, "Setting floatint register through the TC!\n");
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
@@ -419,7 +408,6 @@ template <class Impl>
void
O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
@@ -452,30 +440,6 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val)
}
}
template <class Impl>
void
O3ThreadContext<Impl>::setMicroPC(uint64_t val)
{
cpu->setMicroPC(val, thread->readTid());
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
cpu->squashFromTC(thread->readTid());
}
}
template <class Impl>
void
O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
{
cpu->setNextMicroPC(val, thread->readTid());
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
cpu->squashFromTC(thread->readTid());
}
}
template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)

4
src/cpu/simple/base.cc
View File

@@ -503,7 +503,7 @@ BaseSimpleCPU::advancePC(Fault fault)
} while (oldpc != thread->readPC());
}
Fault
/*Fault
BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
{
// translate to physical address
@@ -536,4 +536,4 @@ BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
}
}
return fault;
}
}*/

6
src/cpu/simple/base.hh
View File

@@ -378,12 +378,8 @@ class BaseSimpleCPU : public BaseCPU
"register access.\n");
}
void setShadowSet(int css) {
panic("Simple CPU models do not support Shadow Sets");
//tc->setShadowSet(css);
}
//Fault CacheOp(uint8_t Op, Addr EA);
Fault CacheOp(uint8_t Op, Addr EA);
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }

4
src/cpu/simple_thread.hh
View File

@@ -368,10 +368,6 @@ class SimpleThread : public ThreadState
void setStCondFailures(unsigned sc_failures)
{ storeCondFailures = sc_failures; }
void setShadowSet(int css, int tid=0) {
regs.setShadowSet(css);
}
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{

14
src/cpu/thread_context.hh
View File

@@ -150,13 +150,13 @@ class ThreadContext
virtual void activate(int delay = 1) = 0;
/// Set the status to Suspended.
virtual void suspend() = 0;
virtual void suspend(int delay = 0) = 0;
/// Set the status to Unallocated.
virtual void deallocate(int delay = 0) = 0;
/// Set the status to Halted.
virtual void halt() = 0;
virtual void halt(int delay = 0) = 0;
#if FULL_SYSTEM
virtual void dumpFuncProfile() = 0;
@@ -238,8 +238,6 @@ class ThreadContext
virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
virtual void setShadowSet(int css) = 0;
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
virtual unsigned readStCondFailures() = 0;
@@ -335,13 +333,13 @@ class ProxyThreadContext : public ThreadContext
void activate(int delay = 1) { actualTC->activate(delay); }
/// Set the status to Suspended.
void suspend() { actualTC->suspend(); }
void suspend(int delay = 0) { actualTC->suspend(); }
/// Set the status to Unallocated.
void deallocate(int delay = 0) { actualTC->deallocate(); }
/// Set the status to Halted.
void halt() { actualTC->halt(); }
void halt(int delay = 0) { actualTC->halt(); }
#if FULL_SYSTEM
void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
@@ -409,10 +407,6 @@ class ProxyThreadContext : public ThreadContext
void setFloatRegBits(int reg_idx, FloatRegBits val)
{ actualTC->setFloatRegBits(reg_idx, val); }
void setShadowSet(int css){
return actualTC->setShadowSet(css);
}
uint64_t readPC() { return actualTC->readPC(); }
void setPC(uint64_t val) { actualTC->setPC(val); }