python: Apply Black formatter to Python files
The command executed was `black src configs tests util`. Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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committed by
Giacomo Travaglini
parent
1cfaa8da83
commit
787204c92d
@@ -52,15 +52,18 @@ from m5.objects import *
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# Create a system with a Crossbar and a TrafficGenerator as CPU:
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system = System()
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system.membus = IOXBar(width = 16)
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system.physmem = SimpleMemory() # This must be instanciated, even if not needed
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system.cpu = TrafficGen(config_file = "conf/tgen.cfg")
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system.clk_domain = SrcClockDomain(clock = '1.5GHz',
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voltage_domain = VoltageDomain(voltage = '1V'))
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system.membus = IOXBar(width=16)
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system.physmem = (
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SimpleMemory()
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) # This must be instanciated, even if not needed
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system.cpu = TrafficGen(config_file="conf/tgen.cfg")
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system.clk_domain = SrcClockDomain(
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clock="1.5GHz", voltage_domain=VoltageDomain(voltage="1V")
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)
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# Create a external TLM port:
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system.tlm = ExternalSlave()
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system.tlm.addr_ranges = [AddrRange('512MB')]
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system.tlm.addr_ranges = [AddrRange("512MB")]
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system.tlm.port_type = "tlm_slave"
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system.tlm.port_data = "transactor"
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@@ -70,7 +73,7 @@ system.system_port = system.membus.slave
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system.membus.master = system.tlm.port
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# Start the simulation:
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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root = Root(full_system=False, system=system)
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root.system.mem_mode = "timing"
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m5.instantiate()
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m5.simulate() #Simulation time specified later on commandline
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m5.simulate() # Simulation time specified later on commandline
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