python: Apply Black formatter to Python files
The command executed was `black src configs tests util`. Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
committed by
Giacomo Travaglini
Giacomo Travaglini
parent
1cfaa8da83
commit
787204c92d
@@ -56,11 +56,12 @@ from m5.objects.Platform import Platform
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default_tracer = ExeTracer()
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class BaseCPU(ClockedObject):
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type = 'BaseCPU'
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type = "BaseCPU"
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abstract = True
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cxx_header = "cpu/base.hh"
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cxx_class = 'gem5::BaseCPU'
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cxx_class = "gem5::BaseCPU"
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cxx_exports = [
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PyBindMethod("switchOut"),
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@@ -75,7 +76,7 @@ class BaseCPU(ClockedObject):
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@classmethod
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def memory_mode(cls):
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"""Which memory mode does this CPU require?"""
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return 'invalid'
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return "invalid"
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@classmethod
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def require_caches(cls):
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@@ -94,17 +95,21 @@ class BaseCPU(ClockedObject):
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def takeOverFrom(self, old_cpu):
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self._ccObject.takeOverFrom(old_cpu._ccObject)
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system = Param.System(Parent.any, "system object")
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cpu_id = Param.Int(-1, "CPU identifier")
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socket_id = Param.Unsigned(0, "Physical Socket identifier")
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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pwr_gating_latency = Param.Cycles(300,
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"Latency to enter power gating state when all contexts are suspended")
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pwr_gating_latency = Param.Cycles(
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300,
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"Latency to enter power gating state when all contexts are suspended",
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)
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power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\
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"to the OFF power state after all thread are disabled for "\
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"pwr_gating_latency cycles")
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power_gating_on_idle = Param.Bool(
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False,
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"Control whether the core goes "
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"to the OFF power state after all thread are disabled for "
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"pwr_gating_latency cycles",
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)
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Tick to start function trace")
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@@ -113,10 +118,12 @@ class BaseCPU(ClockedObject):
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syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry")
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do_checkpoint_insts = Param.Bool(True,
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"enable checkpoint pseudo instructions")
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do_statistics_insts = Param.Bool(True,
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"enable statistics pseudo instructions")
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do_checkpoint_insts = Param.Bool(
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True, "enable checkpoint pseudo instructions"
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)
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do_statistics_insts = Param.Bool(
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True, "enable statistics pseudo instructions"
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)
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workload = VectorParam.Process([], "processes to run")
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@@ -125,93 +132,105 @@ class BaseCPU(ClockedObject):
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isa = VectorParam.BaseISA([], "ISA instance")
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decoder = VectorParam.InstDecoder([], "Decoder instance")
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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simpoint_start_insts = VectorParam.Counter([],
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"starting instruction counts of simpoints")
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progress_interval = Param.Frequency('0Hz',
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"frequency to print out the progress message")
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max_insts_all_threads = Param.Counter(
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0, "terminate when all threads have reached this inst count"
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)
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max_insts_any_thread = Param.Counter(
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0, "terminate when any thread reaches this inst count"
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)
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simpoint_start_insts = VectorParam.Counter(
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[], "starting instruction counts of simpoints"
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)
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progress_interval = Param.Frequency(
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"0Hz", "frequency to print out the progress message"
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)
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switched_out = Param.Bool(False,
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"Leave the CPU switched out after startup (used when switching " \
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"between CPU models)")
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switched_out = Param.Bool(
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False,
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"Leave the CPU switched out after startup (used when switching "
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"between CPU models)",
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)
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tracer = Param.InstTracer(default_tracer, "Instruction tracer")
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icache_port = RequestPort("Instruction Port")
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dcache_port = RequestPort("Data Port")
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_cached_ports = ['icache_port', 'dcache_port']
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_cached_ports = ["icache_port", "dcache_port"]
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_uncached_interrupt_response_ports = []
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_uncached_interrupt_request_ports = []
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def createInterruptController(self):
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self.interrupts = [
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self.ArchInterrupts() for i in range(self.numThreads)]
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self.ArchInterrupts() for i in range(self.numThreads)
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]
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def connectCachedPorts(self, in_ports):
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for p in self._cached_ports:
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exec('self.%s = in_ports' % p)
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exec("self.%s = in_ports" % p)
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def connectUncachedPorts(self, in_ports, out_ports):
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for p in self._uncached_interrupt_response_ports:
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exec('self.%s = out_ports' % p)
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exec("self.%s = out_ports" % p)
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for p in self._uncached_interrupt_request_ports:
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exec('self.%s = in_ports' % p)
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exec("self.%s = in_ports" % p)
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def connectAllPorts(self, cached_in, uncached_in, uncached_out):
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self.connectCachedPorts(cached_in)
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self.connectUncachedPorts(uncached_in, uncached_out)
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def connectBus(self, bus):
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self.connectAllPorts(bus.cpu_side_ports,
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bus.cpu_side_ports, bus.mem_side_ports)
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self.connectAllPorts(
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bus.cpu_side_ports, bus.cpu_side_ports, bus.mem_side_ports
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)
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def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
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def addPrivateSplitL1Caches(self, ic, dc, iwc=None, dwc=None):
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
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self._cached_ports = ["icache.mem_side", "dcache.mem_side"]
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if iwc and dwc:
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self.itb_walker_cache = iwc
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self.dtb_walker_cache = dwc
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self.mmu.connectWalkerPorts(
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iwc.cpu_side, dwc.cpu_side)
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self._cached_ports += ["itb_walker_cache.mem_side", \
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"dtb_walker_cache.mem_side"]
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self.mmu.connectWalkerPorts(iwc.cpu_side, dwc.cpu_side)
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self._cached_ports += [
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"itb_walker_cache.mem_side",
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"dtb_walker_cache.mem_side",
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]
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else:
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self._cached_ports += self.ArchMMU.walkerPorts()
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# Checker doesn't need its own tlb caches because it does
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# functional accesses only
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if self.checker != NULL:
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self._cached_ports += [ "checker." + port
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for port in self.ArchMMU.walkerPorts() ]
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self._cached_ports += [
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"checker." + port for port in self.ArchMMU.walkerPorts()
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]
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
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xbar=None):
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def addTwoLevelCacheHierarchy(
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self, ic, dc, l2c, iwc=None, dwc=None, xbar=None
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):
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self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
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self.toL2Bus = xbar if xbar else L2XBar()
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self.connectCachedPorts(self.toL2Bus.cpu_side_ports)
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self.l2cache = l2c
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self.toL2Bus.mem_side_ports = self.l2cache.cpu_side
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self._cached_ports = ['l2cache.mem_side']
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self._cached_ports = ["l2cache.mem_side"]
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def createThreads(self):
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# If no ISAs have been created, assume that the user wants the
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# default ISA.
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if len(self.isa) == 0:
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self.isa = [ self.ArchISA() for i in range(self.numThreads) ]
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self.isa = [self.ArchISA() for i in range(self.numThreads)]
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else:
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if len(self.isa) != int(self.numThreads):
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raise RuntimeError("Number of ISA instances doesn't "
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"match thread count")
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raise RuntimeError(
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"Number of ISA instances doesn't " "match thread count"
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)
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if len(self.decoder) != 0:
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raise RuntimeError("Decoders should not be set up manually")
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self.decoder = list([ self.ArchDecoder(isa=isa) for isa in self.isa ])
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self.decoder = list([self.ArchDecoder(isa=isa) for isa in self.isa])
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if self.checker != NULL:
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self.checker.createThreads()
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@@ -221,9 +240,9 @@ class BaseCPU(ClockedObject):
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def createPhandleKey(self, thread):
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# This method creates a unique key for this cpu as a function of a
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# certain thread
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return 'CPU-%d-%d-%d' % (self.socket_id, self.cpu_id, thread)
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return "CPU-%d-%d-%d" % (self.socket_id, self.cpu_id, thread)
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#Generate simple CPU Device Tree structure
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# Generate simple CPU Device Tree structure
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def generateDeviceTree(self, state):
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"""Generate cpu nodes for each thread and the corresponding part of the
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cpu-map node. Note that this implementation does not support clusters
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@@ -235,14 +254,14 @@ class BaseCPU(ClockedObject):
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if bool(self.switched_out):
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return
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cpus_node = FdtNode('cpus')
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cpus_node = FdtNode("cpus")
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cpus_node.append(state.CPUCellsProperty())
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#Special size override of 0
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cpus_node.append(FdtPropertyWords('#size-cells', [0]))
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# Special size override of 0
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cpus_node.append(FdtPropertyWords("#size-cells", [0]))
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# Generate cpu nodes
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for i in range(int(self.numThreads)):
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reg = (int(self.socket_id)<<8) + int(self.cpu_id) + i
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reg = (int(self.socket_id) << 8) + int(self.cpu_id) + i
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node = FdtNode("cpu@%x" % reg)
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node.append(FdtPropertyStrings("device_type", "cpu"))
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node.appendCompatible(["gem5,arm-cpu"])
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@@ -251,8 +270,10 @@ class BaseCPU(ClockedObject):
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if found:
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platform.annotateCpuDeviceNode(node, state)
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else:
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warn("Platform not found for device tree generation; " \
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"system or multiple CPUs may not start")
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warn(
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"Platform not found for device tree generation; "
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"system or multiple CPUs may not start"
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)
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freq = int(self.clk_domain.unproxy(self).clock[0].frequency)
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node.append(FdtPropertyWords("clock-frequency", freq))
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@@ -272,20 +293,23 @@ class BaseCPU(ClockedObject):
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def __init__(self, **kwargs):
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super().__init__(**kwargs)
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self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
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self.power_state.possible_states = ["ON", "CLK_GATED", "OFF"]
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self._cached_ports = self._cached_ports + self.ArchMMU.walkerPorts()
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# Practically speaking, these ports will exist on the x86 interrupt
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# controller class.
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if "pio" in self.ArchInterrupts._ports:
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self._uncached_interrupt_response_ports = \
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self._uncached_interrupt_response_ports = (
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self._uncached_interrupt_response_ports + ["interrupts[0].pio"]
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)
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if "int_responder" in self.ArchInterrupts._ports:
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self._uncached_interrupt_response_ports = \
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self._uncached_interrupt_response_ports + [
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"interrupts[0].int_responder"]
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self._uncached_interrupt_response_ports = (
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self._uncached_interrupt_response_ports
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+ ["interrupts[0].int_responder"]
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)
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if "int_requestor" in self.ArchInterrupts._ports:
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self._uncached_interrupt_request_ports = \
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self._uncached_interrupt_request_ports + [
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"interrupts[0].int_requestor"]
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self._uncached_interrupt_request_ports = (
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self._uncached_interrupt_request_ports
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+ ["interrupts[0].int_requestor"]
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)
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