python: Apply Black formatter to Python files

The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs/learning_gem5/part1/caches.py

@@ -36,13 +36,14 @@ import m5
 from m5.objects import Cache
 
 # Add the common scripts to our path
-m5.util.addToPath('../../')
+m5.util.addToPath("../../")
 
 from common import SimpleOpts
 
 # Some specific options for caches
 # For all options see src/mem/cache/BaseCache.py
 
+
 class L1Cache(Cache):
     """Simple L1 Cache with default values"""
 
@@ -66,14 +67,16 @@ class L1Cache(Cache):
            This must be defined in a subclass"""
         raise NotImplementedError
 
+
 class L1ICache(L1Cache):
     """Simple L1 instruction cache with default values"""
 
     # Set the default size
-    size = '16kB'
+    size = "16kB"
 
-    SimpleOpts.add_option('--l1i_size',
-                          help="L1 instruction cache size. Default: %s" % size)
+    SimpleOpts.add_option(
+        "--l1i_size", help="L1 instruction cache size. Default: %s" % size
+    )
 
     def __init__(self, opts=None):
         super(L1ICache, self).__init__(opts)
@@ -85,14 +88,16 @@ class L1ICache(L1Cache):
         """Connect this cache's port to a CPU icache port"""
         self.cpu_side = cpu.icache_port
 
+
 class L1DCache(L1Cache):
     """Simple L1 data cache with default values"""
 
     # Set the default size
-    size = '64kB'
+    size = "64kB"
 
-    SimpleOpts.add_option('--l1d_size',
-                          help="L1 data cache size. Default: %s" % size)
+    SimpleOpts.add_option(
+        "--l1d_size", help="L1 data cache size. Default: %s" % size
+    )
 
     def __init__(self, opts=None):
         super(L1DCache, self).__init__(opts)
@@ -104,11 +109,12 @@ class L1DCache(L1Cache):
         """Connect this cache's port to a CPU dcache port"""
         self.cpu_side = cpu.dcache_port
 
+
 class L2Cache(Cache):
     """Simple L2 Cache with default values"""
 
     # Default parameters
-    size = '256kB'
+    size = "256kB"
     assoc = 8
     tag_latency = 20
     data_latency = 20
@@ -116,7 +122,9 @@ class L2Cache(Cache):
     mshrs = 20
     tgts_per_mshr = 12
 
-    SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
+    SimpleOpts.add_option(
+        "--l2_size", help="L2 cache size. Default: %s" % size
+    )
 
     def __init__(self, opts=None):
         super(L2Cache, self).__init__()

configs/learning_gem5/part1/simple.py

@@ -37,6 +37,7 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 
 # import the m5 (gem5) library created when gem5 is built
 import m5
+
 # import all of the SimObjects
 from m5.objects import *
 
@@ -45,12 +46,12 @@ system = System()
 
 # Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
-system.clk_domain.clock = '1GHz'
+system.clk_domain.clock = "1GHz"
 system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
-system.mem_mode = 'timing'               # Use timing accesses
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_mode = "timing"  # Use timing accesses
+system.mem_ranges = [AddrRange("512MB")]  # Create an address range
 
 # Create a simple CPU
 system.cpu = TimingSimpleCPU()
@@ -67,7 +68,7 @@ system.cpu.createInterruptController()
 
 # For x86 only, make sure the interrupts are connected to the memory
 # Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+if m5.defines.buildEnv["TARGET_ISA"] == "x86":
     system.cpu.interrupts[0].pio = system.membus.mem_side_ports
     system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
     system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
@@ -82,13 +83,14 @@ system.mem_ctrl.port = system.membus.mem_side_ports
 system.system_port = system.membus.cpu_side_ports
 
 # get ISA for the binary to run.
-isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+isa = str(m5.defines.buildEnv["TARGET_ISA"]).lower()
 
 # Default to running 'hello', use the compiled ISA to find the binary
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
-binary = os.path.join(thispath, '../../../',
-                      'tests/test-progs/hello/bin/', isa, 'linux/hello')
+binary = os.path.join(
+    thispath, "../../../", "tests/test-progs/hello/bin/", isa, "linux/hello"
+)
 
 system.workload = SEWorkload.init_compatible(binary)
 
@@ -102,10 +104,10 @@ system.cpu.workload = process
 system.cpu.createThreads()
 
 # set up the root SimObject and start the simulation
-root = Root(full_system = False, system = system)
+root = Root(full_system=False, system=system)
 # instantiate all of the objects we've created above
 m5.instantiate()
 
 print("Beginning simulation!")
 exit_event = m5.simulate()
-print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
+print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

configs/learning_gem5/part1/two_level.py

@@ -40,11 +40,12 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 
 # import the m5 (gem5) library created when gem5 is built
 import m5
+
 # import all of the SimObjects
 from m5.objects import *
 
 # Add the common scripts to our path
-m5.util.addToPath('../../')
+m5.util.addToPath("../../")
 
 # import the caches which we made
 from caches import *
@@ -53,16 +54,17 @@ from caches import *
 from common import SimpleOpts
 
 # get ISA for the default binary to run. This is mostly for simple testing
-isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+isa = str(m5.defines.buildEnv["TARGET_ISA"]).lower()
 
 # Default to running 'hello', use the compiled ISA to find the binary
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
-default_binary = os.path.join(thispath, '../../../',
-    'tests/test-progs/hello/bin/', isa, 'linux/hello')
+default_binary = os.path.join(
+    thispath, "../../../", "tests/test-progs/hello/bin/", isa, "linux/hello"
+)
 
 # Binary to execute
-SimpleOpts.add_option("binary", nargs='?', default=default_binary)
+SimpleOpts.add_option("binary", nargs="?", default=default_binary)
 
 # Finalize the arguments and grab the args so we can pass it on to our objects
 args = SimpleOpts.parse_args()
@@ -72,12 +74,12 @@ system = System()
 
 # Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
-system.clk_domain.clock = '1GHz'
+system.clk_domain.clock = "1GHz"
 system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
-system.mem_mode = 'timing'               # Use timing accesses
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_mode = "timing"  # Use timing accesses
+system.mem_ranges = [AddrRange("512MB")]  # Create an address range
 
 # Create a simple CPU
 system.cpu = TimingSimpleCPU()
@@ -112,7 +114,7 @@ system.cpu.createInterruptController()
 
 # For x86 only, make sure the interrupts are connected to the memory
 # Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+if m5.defines.buildEnv["TARGET_ISA"] == "x86":
     system.cpu.interrupts[0].pio = system.membus.mem_side_ports
     system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
     system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
@@ -138,10 +140,10 @@ system.cpu.workload = process
 system.cpu.createThreads()
 
 # set up the root SimObject and start the simulation
-root = Root(full_system = False, system = system)
+root = Root(full_system=False, system=system)
 # instantiate all of the objects we've created above
 m5.instantiate()
 
 print("Beginning simulation!")
 exit_event = m5.simulate()
-print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
+print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

configs/learning_gem5/part2/hello_goodbye.py

@@ -36,19 +36,20 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 
 # import the m5 (gem5) library created when gem5 is built
 import m5
+
 # import all of the SimObjects
 from m5.objects import *
 
 # set up the root SimObject and start the simulation
-root = Root(full_system = False)
+root = Root(full_system=False)
 
 # Create an instantiation of the simobject you created
-root.hello = HelloObject(time_to_wait = '2us', number_of_fires = 5)
-root.hello.goodbye_object = GoodbyeObject(buffer_size='100B')
+root.hello = HelloObject(time_to_wait="2us", number_of_fires=5)
+root.hello.goodbye_object = GoodbyeObject(buffer_size="100B")
 
 # instantiate all of the objects we've created above
 m5.instantiate()
 
 print("Beginning simulation!")
 exit_event = m5.simulate()
-print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
+print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

configs/learning_gem5/part2/run_simple.py

@@ -35,11 +35,12 @@ system. Since there are no events, this "simulation" should finish immediately
 
 # import the m5 (gem5) library created when gem5 is built
 import m5
+
 # import all of the SimObjects
 from m5.objects import *
 
 # set up the root SimObject and start the simulation
-root = Root(full_system = False)
+root = Root(full_system=False)
 
 # Create an instantiation of the simobject you created
 root.hello = SimpleObject()
@@ -49,4 +50,4 @@ m5.instantiate()
 
 print("Beginning simulation!")
 exit_event = m5.simulate()
-print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
+print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

configs/learning_gem5/part2/simple_cache.py

@@ -33,6 +33,7 @@ This config file assumes that the x86 ISA was built.
 
 # import the m5 (gem5) library created when gem5 is built
 import m5
+
 # import all of the SimObjects
 from m5.objects import *
 
@@ -41,12 +42,12 @@ system = System()
 
 # Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
-system.clk_domain.clock = '1GHz'
+system.clk_domain.clock = "1GHz"
 system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
-system.mem_mode = 'timing'               # Use timing accesses
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_mode = "timing"  # Use timing accesses
+system.mem_ranges = [AddrRange("512MB")]  # Create an address range
 
 # Create a simple CPU
 system.cpu = TimingSimpleCPU()
@@ -55,7 +56,7 @@ system.cpu = TimingSimpleCPU()
 system.membus = SystemXBar()
 
 # Create a simple cache
-system.cache = SimpleCache(size='1kB')
+system.cache = SimpleCache(size="1kB")
 
 # Connect the I and D cache ports of the CPU to the memobj.
 # Since cpu_side is a vector port, each time one of these is connected, it will
@@ -86,8 +87,9 @@ process = Process()
 # Set the command
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
-binpath = os.path.join(thispath, '../../../',
-                       'tests/test-progs/hello/bin/x86/linux/hello')
+binpath = os.path.join(
+    thispath, "../../../", "tests/test-progs/hello/bin/x86/linux/hello"
+)
 # cmd is a list which begins with the executable (like argv)
 process.cmd = [binpath]
 # Set the cpu to use the process as its workload and create thread contexts
@@ -97,10 +99,10 @@ system.cpu.createThreads()
 system.workload = SEWorkload.init_compatible(binpath)
 
 # set up the root SimObject and start the simulation
-root = Root(full_system = False, system = system)
+root = Root(full_system=False, system=system)
 # instantiate all of the objects we've created above
 m5.instantiate()
 
 print("Beginning simulation!")
 exit_event = m5.simulate()
-print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
+print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

configs/learning_gem5/part2/simple_memobj.py

@@ -33,6 +33,7 @@ This config file assumes that the x86 ISA was built.
 
 # import the m5 (gem5) library created when gem5 is built
 import m5
+
 # import all of the SimObjects
 from m5.objects import *
 
@@ -41,12 +42,12 @@ system = System()
 
 # Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
-system.clk_domain.clock = '1GHz'
+system.clk_domain.clock = "1GHz"
 system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
-system.mem_mode = 'timing'               # Use timing accesses
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_mode = "timing"  # Use timing accesses
+system.mem_ranges = [AddrRange("512MB")]  # Create an address range
 
 # Create a simple CPU
 system.cpu = TimingSimpleCPU()
@@ -84,8 +85,9 @@ process = Process()
 # Set the command
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
-binpath = os.path.join(thispath, '../../../',
-                       'tests/test-progs/hello/bin/x86/linux/hello')
+binpath = os.path.join(
+    thispath, "../../../", "tests/test-progs/hello/bin/x86/linux/hello"
+)
 # cmd is a list which begins with the executable (like argv)
 process.cmd = [binpath]
 # Set the cpu to use the process as its workload and create thread contexts
@@ -95,10 +97,10 @@ system.cpu.createThreads()
 system.workload = SEWorkload.init_compatible(binpath)
 
 # set up the root SimObject and start the simulation
-root = Root(full_system = False, system = system)
+root = Root(full_system=False, system=system)
 # instantiate all of the objects we've created above
 m5.instantiate()
 
 print("Beginning simulation!")
 exit_event = m5.simulate()
-print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
+print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

configs/learning_gem5/part3/msi_caches.py

@@ -42,10 +42,10 @@ from m5.util import fatal, panic
 
 from m5.objects import *
 
-class MyCacheSystem(RubySystem):
 
+class MyCacheSystem(RubySystem):
     def __init__(self):
-        if buildEnv['PROTOCOL'] != 'MSI':
+        if buildEnv["PROTOCOL"] != "MSI":
             fatal("This system assumes MSI from learning gem5!")
 
         super(MyCacheSystem, self).__init__()
@@ -70,22 +70,26 @@ class MyCacheSystem(RubySystem):
         # customized depending on the topology/network requirements.
         # Create one controller for each L1 cache (and the cache mem obj.)
         # Create a single directory controller (Really the memory cntrl)
-        self.controllers = \
-            [L1Cache(system, self, cpu) for cpu in cpus] + \
-            [DirController(self, system.mem_ranges, mem_ctrls)]
+        self.controllers = [L1Cache(system, self, cpu) for cpu in cpus] + [
+            DirController(self, system.mem_ranges, mem_ctrls)
+        ]
 
         # Create one sequencer per CPU. In many systems this is more
         # complicated since you have to create sequencers for DMA controllers
         # and other controllers, too.
-        self.sequencers = [RubySequencer(version = i,
-                                # I/D cache is combined and grab from ctrl
-                                dcache = self.controllers[i].cacheMemory,
-                                clk_domain = self.controllers[i].clk_domain,
-                                ) for i in range(len(cpus))]
+        self.sequencers = [
+            RubySequencer(
+                version=i,
+                # I/D cache is combined and grab from ctrl
+                dcache=self.controllers[i].cacheMemory,
+                clk_domain=self.controllers[i].clk_domain,
+            )
+            for i in range(len(cpus))
+        ]
 
         # We know that we put the controllers in an order such that the first
         # N of them are the L1 caches which need a sequencer pointer
-        for i,c in enumerate(self.controllers[0:len(self.sequencers)]):
+        for i, c in enumerate(self.controllers[0 : len(self.sequencers)]):
             c.sequencer = self.sequencers[i]
 
         self.num_of_sequencers = len(self.sequencers)
@@ -101,16 +105,17 @@ class MyCacheSystem(RubySystem):
         system.system_port = self.sys_port_proxy.in_ports
 
         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
-        for i,cpu in enumerate(cpus):
+        for i, cpu in enumerate(cpus):
             self.sequencers[i].connectCpuPorts(cpu)
 
 
 class L1Cache(L1Cache_Controller):
 
     _version = 0
+
     @classmethod
     def versionCount(cls):
-        cls._version += 1 # Use count for this particular type
+        cls._version += 1  # Use count for this particular type
         return cls._version - 1
 
     def __init__(self, system, ruby_system, cpu):
@@ -121,9 +126,9 @@ class L1Cache(L1Cache_Controller):
 
         self.version = self.versionCount()
         # This is the cache memory object that stores the cache data and tags
-        self.cacheMemory = RubyCache(size = '16kB',
-                               assoc = 8,
-                               start_index_bit = self.getBlockSizeBits(system))
+        self.cacheMemory = RubyCache(
+            size="16kB", assoc=8, start_index_bit=self.getBlockSizeBits(system)
+        )
         self.clk_domain = cpu.clk_domain
         self.send_evictions = self.sendEvicts(cpu)
         self.ruby_system = ruby_system
@@ -131,7 +136,7 @@ class L1Cache(L1Cache_Controller):
 
     def getBlockSizeBits(self, system):
         bits = int(math.log(system.cache_line_size, 2))
-        if 2**bits != system.cache_line_size.value:
+        if 2 ** bits != system.cache_line_size.value:
             panic("Cache line size not a power of 2!")
         return bits
 
@@ -142,8 +147,7 @@ class L1Cache(L1Cache_Controller):
            2. The x86 mwait instruction is built on top of coherence
            3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or \
-           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
+        if type(cpu) is DerivO3CPU or buildEnv["TARGET_ISA"] in ("x86", "arm"):
             return True
         return False
 
@@ -160,21 +164,23 @@ class L1Cache(L1Cache_Controller):
         # mean the same thing as normal gem5 ports. If a MessageBuffer
         # is a "to" buffer (i.e., out) then you use the "out_port",
         # otherwise, the in_port.
-        self.requestToDir = MessageBuffer(ordered = True)
+        self.requestToDir = MessageBuffer(ordered=True)
         self.requestToDir.out_port = ruby_system.network.in_port
-        self.responseToDirOrSibling = MessageBuffer(ordered = True)
+        self.responseToDirOrSibling = MessageBuffer(ordered=True)
         self.responseToDirOrSibling.out_port = ruby_system.network.in_port
-        self.forwardFromDir = MessageBuffer(ordered = True)
+        self.forwardFromDir = MessageBuffer(ordered=True)
         self.forwardFromDir.in_port = ruby_system.network.out_port
-        self.responseFromDirOrSibling = MessageBuffer(ordered = True)
+        self.responseFromDirOrSibling = MessageBuffer(ordered=True)
         self.responseFromDirOrSibling.in_port = ruby_system.network.out_port
 
+
 class DirController(Directory_Controller):
 
     _version = 0
+
     @classmethod
     def versionCount(cls):
-        cls._version += 1 # Use count for this particular type
+        cls._version += 1  # Use count for this particular type
         return cls._version - 1
 
     def __init__(self, ruby_system, ranges, mem_ctrls):
@@ -192,14 +198,14 @@ class DirController(Directory_Controller):
         self.connectQueues(ruby_system)
 
     def connectQueues(self, ruby_system):
-        self.requestFromCache = MessageBuffer(ordered = True)
+        self.requestFromCache = MessageBuffer(ordered=True)
         self.requestFromCache.in_port = ruby_system.network.out_port
-        self.responseFromCache = MessageBuffer(ordered = True)
+        self.responseFromCache = MessageBuffer(ordered=True)
         self.responseFromCache.in_port = ruby_system.network.out_port
 
-        self.responseToCache = MessageBuffer(ordered = True)
+        self.responseToCache = MessageBuffer(ordered=True)
         self.responseToCache.out_port = ruby_system.network.in_port
-        self.forwardToCache = MessageBuffer(ordered = True)
+        self.forwardToCache = MessageBuffer(ordered=True)
         self.forwardToCache.out_port = ruby_system.network.in_port
 
         # These are other special message buffers. They are used to send
@@ -209,6 +215,7 @@ class DirController(Directory_Controller):
         self.requestToMemory = MessageBuffer()
         self.responseFromMemory = MessageBuffer()
 
+
 class MyNetwork(SimpleNetwork):
     """A simple point-to-point network. This doesn't not use garnet.
     """
@@ -223,13 +230,14 @@ class MyNetwork(SimpleNetwork):
            together in a point-to-point network.
         """
         # Create one router/switch per controller in the system
-        self.routers = [Switch(router_id = i) for i in range(len(controllers))]
+        self.routers = [Switch(router_id=i) for i in range(len(controllers))]
 
         # Make a link from each controller to the router. The link goes
         # externally to the network.
-        self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
-                                        int_node=self.routers[i])
-                          for i, c in enumerate(controllers)]
+        self.ext_links = [
+            SimpleExtLink(link_id=i, ext_node=c, int_node=self.routers[i])
+            for i, c in enumerate(controllers)
+        ]
 
         # Make an "internal" link (internal to the network) between every pair
         # of routers.
@@ -237,9 +245,10 @@ class MyNetwork(SimpleNetwork):
         int_links = []
         for ri in self.routers:
             for rj in self.routers:
-                if ri == rj: continue # Don't connect a router to itself!
+                if ri == rj:
+                    continue  # Don't connect a router to itself!
                 link_count += 1
-                int_links.append(SimpleIntLink(link_id = link_count,
-                                                    src_node = ri,
-                                                    dst_node = rj))
+                int_links.append(
+                    SimpleIntLink(link_id=link_count, src_node=ri, dst_node=rj)
+                )
         self.int_links = int_links

configs/learning_gem5/part3/ruby_caches_MI_example.py

@@ -44,10 +44,10 @@ from m5.util import fatal, panic
 
 from m5.objects import *
 
-class MyCacheSystem(RubySystem):
 
+class MyCacheSystem(RubySystem):
     def __init__(self):
-        if buildEnv['PROTOCOL'] != 'MI_example':
+        if buildEnv["PROTOCOL"] != "MI_example":
             fatal("This system assumes MI_example!")
 
         super(MyCacheSystem, self).__init__()
@@ -70,20 +70,24 @@ class MyCacheSystem(RubySystem):
         # customized depending on the topology/network requirements.
         # Create one controller for each L1 cache (and the cache mem obj.)
         # Create a single directory controller (Really the memory cntrl)
-        self.controllers = \
-            [L1Cache(system, self, cpu) for cpu in cpus] + \
-            [DirController(self, system.mem_ranges, mem_ctrls)]
+        self.controllers = [L1Cache(system, self, cpu) for cpu in cpus] + [
+            DirController(self, system.mem_ranges, mem_ctrls)
+        ]
 
         # Create one sequencer per CPU. In many systems this is more
         # complicated since you have to create sequencers for DMA controllers
         # and other controllers, too.
-        self.sequencers = [RubySequencer(version = i,
-                                # I/D cache is combined and grab from ctrl
-                                dcache = self.controllers[i].cacheMemory,
-                                clk_domain = self.controllers[i].clk_domain,
-                                ) for i in range(len(cpus))]
+        self.sequencers = [
+            RubySequencer(
+                version=i,
+                # I/D cache is combined and grab from ctrl
+                dcache=self.controllers[i].cacheMemory,
+                clk_domain=self.controllers[i].clk_domain,
+            )
+            for i in range(len(cpus))
+        ]
 
-        for i,c in enumerate(self.controllers[0:len(cpus)]):
+        for i, c in enumerate(self.controllers[0 : len(cpus)]):
             c.sequencer = self.sequencers[i]
 
         self.num_of_sequencers = len(self.sequencers)
@@ -99,15 +103,17 @@ class MyCacheSystem(RubySystem):
         system.system_port = self.sys_port_proxy.in_ports
 
         # Connect the cpu's cache, interrupt, and TLB ports to Ruby
-        for i,cpu in enumerate(cpus):
+        for i, cpu in enumerate(cpus):
             self.sequencers[i].connectCpuPorts(cpu)
 
+
 class L1Cache(L1Cache_Controller):
 
     _version = 0
+
     @classmethod
     def versionCount(cls):
-        cls._version += 1 # Use count for this particular type
+        cls._version += 1  # Use count for this particular type
         return cls._version - 1
 
     def __init__(self, system, ruby_system, cpu):
@@ -118,9 +124,9 @@ class L1Cache(L1Cache_Controller):
 
         self.version = self.versionCount()
         # This is the cache memory object that stores the cache data and tags
-        self.cacheMemory = RubyCache(size = '16kB',
-                               assoc = 8,
-                               start_index_bit = self.getBlockSizeBits(system))
+        self.cacheMemory = RubyCache(
+            size="16kB", assoc=8, start_index_bit=self.getBlockSizeBits(system)
+        )
         self.clk_domain = cpu.clk_domain
         self.send_evictions = self.sendEvicts(cpu)
         self.ruby_system = ruby_system
@@ -128,7 +134,7 @@ class L1Cache(L1Cache_Controller):
 
     def getBlockSizeBits(self, system):
         bits = int(math.log(system.cache_line_size, 2))
-        if 2**bits != system.cache_line_size.value:
+        if 2 ** bits != system.cache_line_size.value:
             panic("Cache line size not a power of 2!")
         return bits
 
@@ -139,8 +145,7 @@ class L1Cache(L1Cache_Controller):
            2. The x86 mwait instruction is built on top of coherence
            3. The local exclusive monitor in ARM systems
         """
-        if type(cpu) is DerivO3CPU or \
-           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
+        if type(cpu) is DerivO3CPU or buildEnv["TARGET_ISA"] in ("x86", "arm"):
             return True
         return False
 
@@ -148,21 +153,23 @@ class L1Cache(L1Cache_Controller):
         """Connect all of the queues for this controller.
         """
         self.mandatoryQueue = MessageBuffer()
-        self.requestFromCache = MessageBuffer(ordered = True)
+        self.requestFromCache = MessageBuffer(ordered=True)
         self.requestFromCache.out_port = ruby_system.network.in_port
-        self.responseFromCache = MessageBuffer(ordered = True)
+        self.responseFromCache = MessageBuffer(ordered=True)
         self.responseFromCache.out_port = ruby_system.network.in_port
-        self.forwardToCache = MessageBuffer(ordered = True)
+        self.forwardToCache = MessageBuffer(ordered=True)
         self.forwardToCache.in_port = ruby_system.network.out_port
-        self.responseToCache = MessageBuffer(ordered = True)
+        self.responseToCache = MessageBuffer(ordered=True)
         self.responseToCache.in_port = ruby_system.network.out_port
 
+
 class DirController(Directory_Controller):
 
     _version = 0
+
     @classmethod
     def versionCount(cls):
-        cls._version += 1 # Use count for this particular type
+        cls._version += 1  # Use count for this particular type
         return cls._version - 1
 
     def __init__(self, ruby_system, ranges, mem_ctrls):
@@ -180,20 +187,21 @@ class DirController(Directory_Controller):
         self.connectQueues(ruby_system)
 
     def connectQueues(self, ruby_system):
-        self.requestToDir = MessageBuffer(ordered = True)
+        self.requestToDir = MessageBuffer(ordered=True)
         self.requestToDir.in_port = ruby_system.network.out_port
-        self.dmaRequestToDir = MessageBuffer(ordered = True)
+        self.dmaRequestToDir = MessageBuffer(ordered=True)
         self.dmaRequestToDir.in_port = ruby_system.network.out_port
 
         self.responseFromDir = MessageBuffer()
         self.responseFromDir.out_port = ruby_system.network.in_port
-        self.dmaResponseFromDir = MessageBuffer(ordered = True)
+        self.dmaResponseFromDir = MessageBuffer(ordered=True)
         self.dmaResponseFromDir.out_port = ruby_system.network.in_port
         self.forwardFromDir = MessageBuffer()
         self.forwardFromDir.out_port = ruby_system.network.in_port
         self.requestToMemory = MessageBuffer()
         self.responseFromMemory = MessageBuffer()
 
+
 class MyNetwork(SimpleNetwork):
     """A simple point-to-point network. This doesn't not use garnet.
     """
@@ -208,13 +216,14 @@ class MyNetwork(SimpleNetwork):
            together in a point-to-point network.
         """
         # Create one router/switch per controller in the system
-        self.routers = [Switch(router_id = i) for i in range(len(controllers))]
+        self.routers = [Switch(router_id=i) for i in range(len(controllers))]
 
         # Make a link from each controller to the router. The link goes
         # externally to the network.
-        self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
-                                        int_node=self.routers[i])
-                          for i, c in enumerate(controllers)]
+        self.ext_links = [
+            SimpleExtLink(link_id=i, ext_node=c, int_node=self.routers[i])
+            for i, c in enumerate(controllers)
+        ]
 
         # Make an "internal" link (internal to the network) between every pair
         # of routers.
@@ -222,9 +231,10 @@ class MyNetwork(SimpleNetwork):
         int_links = []
         for ri in self.routers:
             for rj in self.routers:
-                if ri == rj: continue # Don't connect a router to itself!
+                if ri == rj:
+                    continue  # Don't connect a router to itself!
                 link_count += 1
-                int_links.append(SimpleIntLink(link_id = link_count,
-                                                    src_node = ri,
-                                                    dst_node = rj))
+                int_links.append(
+                    SimpleIntLink(link_id=link_count, src_node=ri, dst_node=rj)
+                )
         self.int_links = int_links

configs/learning_gem5/part3/ruby_test.py

@@ -36,6 +36,7 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 
 # import the m5 (gem5) library created when gem5 is built
 import m5
+
 # import all of the SimObjects
 from m5.objects import *
 
@@ -46,17 +47,17 @@ system = System()
 
 # Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
-system.clk_domain.clock = '1GHz'
+system.clk_domain.clock = "1GHz"
 system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
-system.mem_mode = 'timing'               # Use timing accesses
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_mode = "timing"  # Use timing accesses
+system.mem_ranges = [AddrRange("512MB")]  # Create an address range
 
 # Create the tester
-system.tester = RubyTester(checks_to_complete = 100,
-                           wakeup_frequency = 10,
-                           num_cpus = 2)
+system.tester = RubyTester(
+    checks_to_complete=100, wakeup_frequency=10, num_cpus=2
+)
 
 # Create a simple memory controller and connect it to the membus
 system.mem_ctrl = SimpleMemory(latency="50ns", bandwidth="0GB/s")
@@ -67,16 +68,16 @@ system.caches = TestCacheSystem()
 system.caches.setup(system, system.tester, [system.mem_ctrl])
 
 # set up the root SimObject and start the simulation
-root = Root(full_system = False, system = system)
+root = Root(full_system=False, system=system)
 
 # Not much point in this being higher than the L1 latency
-m5.ticks.setGlobalFrequency('1ns')
+m5.ticks.setGlobalFrequency("1ns")
 
 # instantiate all of the objects we've created above
 m5.instantiate()
 
 print("Beginning simulation!")
 exit_event = m5.simulate()
-print('Exiting @ tick {} because {}'.format(
-         m5.curTick(), exit_event.getCause())
-     )
+print(
+    "Exiting @ tick {} because {}".format(m5.curTick(), exit_event.getCause())
+)

configs/learning_gem5/part3/simple_ruby.py

@@ -39,11 +39,12 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
 
 # import the m5 (gem5) library created when gem5 is built
 import m5
+
 # import all of the SimObjects
 from m5.objects import *
 
 # Needed for running C++ threads
-m5.util.addToPath('../../')
+m5.util.addToPath("../../")
 from common.FileSystemConfig import config_filesystem
 
 # You can import ruby_caches_MI_example to use the MI_example protocol instead
@@ -55,12 +56,12 @@ system = System()
 
 # Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
-system.clk_domain.clock = '1GHz'
+system.clk_domain.clock = "1GHz"
 system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
-system.mem_mode = 'timing'               # Use timing accesses
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_mode = "timing"  # Use timing accesses
+system.mem_ranges = [AddrRange("512MB")]  # Create an address range
 
 # Create a pair of simple CPUs
 system.cpu = [TimingSimpleCPU() for i in range(2)]
@@ -79,13 +80,18 @@ system.caches = MyCacheSystem()
 system.caches.setup(system, system.cpu, [system.mem_ctrl])
 
 # get ISA for the binary to run.
-isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+isa = str(m5.defines.buildEnv["TARGET_ISA"]).lower()
 
 # Run application and use the compiled ISA to find the binary
 # grab the specific path to the binary
 thispath = os.path.dirname(os.path.realpath(__file__))
-binary = os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/',
-                      isa, 'linux/threads')
+binary = os.path.join(
+    thispath,
+    "../../../",
+    "tests/test-progs/threads/bin/",
+    isa,
+    "linux/threads",
+)
 
 # Create a process for a simple "multi-threaded" application
 process = Process()
@@ -103,12 +109,12 @@ system.workload = SEWorkload.init_compatible(binary)
 config_filesystem(system)
 
 # set up the root SimObject and start the simulation
-root = Root(full_system = False, system = system)
+root = Root(full_system=False, system=system)
 # instantiate all of the objects we've created above
 m5.instantiate()
 
 print("Beginning simulation!")
 exit_event = m5.simulate()
-print('Exiting @ tick {} because {}'.format(
-         m5.curTick(), exit_event.getCause())
-     )
+print(
+    "Exiting @ tick {} because {}".format(m5.curTick(), exit_event.getCause())
+)

configs/learning_gem5/part3/test_caches.py

@@ -42,10 +42,10 @@ from m5.objects import *
 
 from msi_caches import L1Cache, DirController, MyNetwork
 
-class TestCacheSystem(RubySystem):
 
+class TestCacheSystem(RubySystem):
     def __init__(self):
-        if buildEnv['PROTOCOL'] != 'MSI':
+        if buildEnv["PROTOCOL"] != "MSI":
             fatal("This system assumes MSI from learning gem5!")
 
         super(TestCacheSystem, self).__init__()
@@ -67,17 +67,21 @@ class TestCacheSystem(RubySystem):
         self.number_of_virtual_networks = 3
         self.network.number_of_virtual_networks = 3
 
-        self.controllers = \
-            [L1Cache(system, self, self) for i in range(num_testers)] + \
-            [DirController(self, system.mem_ranges, mem_ctrls)]
+        self.controllers = [
+            L1Cache(system, self, self) for i in range(num_testers)
+        ] + [DirController(self, system.mem_ranges, mem_ctrls)]
 
-        self.sequencers = [RubySequencer(version = i,
-                              # I/D cache is combined and grab from ctrl
-                              dcache = self.controllers[i].cacheMemory,
-                              clk_domain = self.clk_domain,
-                              ) for i in range(num_testers)]
+        self.sequencers = [
+            RubySequencer(
+                version=i,
+                # I/D cache is combined and grab from ctrl
+                dcache=self.controllers[i].cacheMemory,
+                clk_domain=self.clk_domain,
+            )
+            for i in range(num_testers)
+        ]
 
-        for i,c in enumerate(self.controllers[0:len(self.sequencers)]):
+        for i, c in enumerate(self.controllers[0 : len(self.sequencers)]):
             c.sequencer = self.sequencers[i]
 
         self.num_of_sequencers = len(self.sequencers)