python: Apply Black formatter to Python files

The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
2022-07-05 11:02:25 -07:00
committed by Giacomo Travaglini
parent 1cfaa8da83
commit 787204c92d
980 changed files with 35668 additions and 22233 deletions

View File

@@ -31,7 +31,7 @@ from m5.defines import buildEnv
from m5.util import addToPath
import os, argparse, sys
addToPath('../')
addToPath("../")
from common import Options
from ruby import Ruby
@@ -44,16 +44,28 @@ m5_root = os.path.dirname(config_root)
parser = argparse.ArgumentParser()
Options.addNoISAOptions(parser)
parser.add_argument("--requests", metavar="N", default=100,
help="Stop after N requests")
parser.add_argument("-f", "--wakeup_freq", metavar="N", default=10,
help="Wakeup every N cycles")
parser.add_argument("--test-type", default="SeriesGetx",
choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed",
"Invalidate"],
help = "Type of test")
parser.add_argument("--percent-writes", type=int, default=100,
help="percentage of accesses that should be writes")
parser.add_argument(
"--requests", metavar="N", default=100, help="Stop after N requests"
)
parser.add_argument(
"-f",
"--wakeup_freq",
metavar="N",
default=10,
help="Wakeup every N cycles",
)
parser.add_argument(
"--test-type",
default="SeriesGetx",
choices=["SeriesGetx", "SeriesGets", "SeriesGetMixed", "Invalidate"],
help="Type of test",
)
parser.add_argument(
"--percent-writes",
type=int,
default=100,
help="percentage of accesses that should be writes",
)
#
# Add the ruby specific and protocol specific args
@@ -65,47 +77,53 @@ args = parser.parse_args()
# Select the direct test generator
#
if args.test_type == "SeriesGetx":
generator = SeriesRequestGenerator(num_cpus = args.num_cpus,
percent_writes = 100)
generator = SeriesRequestGenerator(
num_cpus=args.num_cpus, percent_writes=100
)
elif args.test_type == "SeriesGets":
generator = SeriesRequestGenerator(num_cpus = args.num_cpus,
percent_writes = 0)
generator = SeriesRequestGenerator(
num_cpus=args.num_cpus, percent_writes=0
)
elif args.test_type == "SeriesGetMixed":
generator = SeriesRequestGenerator(num_cpus = args.num_cpus,
percent_writes = args.percent_writes)
generator = SeriesRequestGenerator(
num_cpus=args.num_cpus, percent_writes=args.percent_writes
)
elif args.test_type == "Invalidate":
generator = InvalidateGenerator(num_cpus = args.num_cpus)
generator = InvalidateGenerator(num_cpus=args.num_cpus)
else:
print("Error: unknown direct test generator")
sys.exit(1)
# Create the M5 system.
system = System(mem_ranges = [AddrRange(args.mem_size)])
system = System(mem_ranges=[AddrRange(args.mem_size)])
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = args.sys_voltage)
system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
system.clk_domain = SrcClockDomain(clock = args.sys_clock,
voltage_domain = system.voltage_domain)
system.clk_domain = SrcClockDomain(
clock=args.sys_clock, voltage_domain=system.voltage_domain
)
# Create the ruby random tester
system.cpu = RubyDirectedTester(requests_to_complete = args.requests,
generator = generator)
system.cpu = RubyDirectedTester(
requests_to_complete=args.requests, generator=generator
)
# the ruby tester reuses num_cpus to specify the
# number of cpu ports connected to the tester object, which
# is stored in system.cpu. because there is only ever one
# tester object, num_cpus is not necessarily equal to the
# size of system.cpu
cpu_list = [ system.cpu ] * args.num_cpus
cpu_list = [system.cpu] * args.num_cpus
Ruby.create_system(args, False, system, cpus=cpu_list)
# Since Ruby runs at an independent frequency, create a seperate clock
system.ruby.clk_domain = SrcClockDomain(clock = args.ruby_clock,
voltage_domain = system.voltage_domain)
system.ruby.clk_domain = SrcClockDomain(
clock=args.ruby_clock, voltage_domain=system.voltage_domain
)
assert(args.num_cpus == len(system.ruby._cpu_ports))
assert args.num_cpus == len(system.ruby._cpu_ports)
for ruby_port in system.ruby._cpu_ports:
#
@@ -117,11 +135,11 @@ for ruby_port in system.ruby._cpu_ports:
# run simulation
# -----------------------
root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"
# Not much point in this being higher than the L1 latency
m5.ticks.setGlobalFrequency('1ns')
m5.ticks.setGlobalFrequency("1ns")
# instantiate configuration
m5.instantiate()
@@ -129,4 +147,4 @@ m5.instantiate()
# simulate until program terminates
exit_event = m5.simulate(args.abs_max_tick)
print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
print("Exiting @ tick", m5.curTick(), "because", exit_event.getCause())