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python: Apply Black formatter to Python files

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The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
2022-07-05 11:02:25 -07:00
committed by Giacomo Travaglini
parent 1cfaa8da83
commit 787204c92d
980 changed files with 35668 additions and 22233 deletions
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85
configs/dram/lat_mem_rd.py
View File

@@ -42,11 +42,11 @@ from m5.objects import *
from m5.util import addToPath
from m5.stats import periodicStatDump
addToPath('../')
addToPath("../")
from common import ObjectList
from common import MemConfig
addToPath('../../util')
addToPath("../../util")
import protolib
# this script is helpful to observe the memory latency for various
@@ -61,8 +61,15 @@ try:
except:
print("Did not find packet proto definitions, attempting to generate")
from subprocess import call
error = call(['protoc', '--python_out=configs/dram',
'--proto_path=src/proto', 'src/proto/packet.proto'])
error = call(
[
"protoc",
"--python_out=configs/dram",
"--proto_path=src/proto",
"src/proto/packet.proto",
]
)
if not error:
print("Generated packet proto definitions")
@@ -79,24 +86,34 @@ except:
parser = argparse.ArgumentParser()
parser.add_argument("--mem-type", default="DDR3_1600_8x8",
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_argument("--mem-size", action="store", type=str,
default="16MB",
help="Specify the memory size")
parser.add_argument("--reuse-trace", action="store_true",
help="Prevent generation of traces and reuse existing")
parser.add_argument(
"--mem-type",
default="DDR3_1600_8x8",
choices=ObjectList.mem_list.get_names(),
help="type of memory to use",
)
parser.add_argument(
"--mem-size",
action="store",
type=str,
default="16MB",
help="Specify the memory size",
)
parser.add_argument(
"--reuse-trace",
action="store_true",
help="Prevent generation of traces and reuse existing",
)
args = parser.parse_args()
# start by creating the system itself, using a multi-layer 2.0 GHz
# crossbar, delivering 64 bytes / 3 cycles (one header cycle) which
# amounts to 42.7 GByte/s per layer and thus per port
system = System(membus = SystemXBar(width = 32))
system.clk_domain = SrcClockDomain(clock = '2.0GHz',
voltage_domain =
VoltageDomain(voltage = '1V'))
system = System(membus=SystemXBar(width=32))
system.clk_domain = SrcClockDomain(
clock="2.0GHz", voltage_domain=VoltageDomain(voltage="1V")
)
mem_range = AddrRange(args.mem_size)
system.mem_ranges = [mem_range]
@@ -122,12 +139,12 @@ for ctrl in system.mem_ctrls:
if isinstance(ctrl, m5.objects.MemCtrl):
# make the DRAM refresh interval sufficiently infinite to avoid
# latency spikes
ctrl.tREFI = '100s'
ctrl.tREFI = "100s"
# use the same concept as the utilisation sweep, and print the config
# so that we can later read it in
cfg_file_name = os.path.join(m5.options.outdir, "lat_mem_rd.cfg")
cfg_file = open(cfg_file_name, 'w')
cfg_file = open(cfg_file_name, "w")
# set an appropriate burst length in bytes
burst_size = 64
@@ -137,6 +154,7 @@ system.cache_line_size = burst_size
def is_pow2(num):
return num != 0 and ((num & (num - 1)) == 0)
# assume we start every range at 0
max_range = int(mem_range.end)
@@ -164,7 +182,7 @@ itt = 150 * 1000
# the actual measurement
def create_trace(filename, max_addr, burst_size, itt):
try:
proto_out = gzip.open(filename, 'wb')
proto_out = gzip.open(filename, "wb")
except IOError:
print("Failed to open ", filename, " for writing")
exit(-1)
@@ -184,6 +202,7 @@ def create_trace(filename, max_addr, burst_size, itt):
addrs = list(range(0, max_addr, burst_size))
import random
random.shuffle(addrs)
tick = 0
@@ -202,6 +221,7 @@ def create_trace(filename, max_addr, burst_size, itt):
proto_out.close()
# this will take a while, so keep the user informed
print("Generating traces, please wait...")
@@ -211,22 +231,23 @@ period = int(itt * (max_range / burst_size))
# now we create the states for each range
for r in ranges:
filename = os.path.join(m5.options.outdir,
'lat_mem_rd%d.trc.gz' % nxt_range)
filename = os.path.join(
m5.options.outdir, "lat_mem_rd%d.trc.gz" % nxt_range
)
if not args.reuse_trace:
# create the actual random trace for this range
create_trace(filename, r, burst_size, itt)
# the warming state
cfg_file.write("STATE %d %d TRACE %s 0\n" %
(nxt_state, period, filename))
cfg_file.write("STATE %d %d TRACE %s 0\n" % (nxt_state, period, filename))
nxt_state = nxt_state + 1
# the measuring states
for i in range(iterations):
cfg_file.write("STATE %d %d TRACE %s 0\n" %
(nxt_state, period, filename))
cfg_file.write(
"STATE %d %d TRACE %s 0\n" % (nxt_state, period, filename)
)
nxt_state = nxt_state + 1
nxt_range = nxt_range + 1
@@ -242,8 +263,7 @@ cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
cfg_file.close()
# create a traffic generator, and point it to the file we just created
system.tgen = TrafficGen(config_file = cfg_file_name,
progress_check = '10s')
system.tgen = TrafficGen(config_file=cfg_file_name, progress_check="10s")
# add a communication monitor
system.monitor = CommMonitor()
@@ -267,19 +287,20 @@ class L3Cache(Cache):
tgts_per_mshr = 12
write_buffers = 16
# note that everything is in the same clock domain, 2.0 GHz as
# specified above
system.l1cache = L1_DCache(size = '64kB')
system.l1cache = L1_DCache(size="64kB")
system.monitor.mem_side_port = system.l1cache.cpu_side
system.l2cache = L2Cache(size = '512kB', writeback_clean = True)
system.l2cache = L2Cache(size="512kB", writeback_clean=True)
system.l2cache.xbar = L2XBar()
system.l1cache.mem_side = system.l2cache.xbar.cpu_side_ports
system.l2cache.cpu_side = system.l2cache.xbar.mem_side_ports
# make the L3 mostly exclusive, and correspondingly ensure that the L2
# writes back also clean lines to the L3
system.l3cache = L3Cache(size = '4MB', clusivity = 'mostly_excl')
system.l3cache = L3Cache(size="4MB", clusivity="mostly_excl")
system.l3cache.xbar = L2XBar()
system.l2cache.mem_side = system.l3cache.xbar.cpu_side_ports
system.l3cache.cpu_side = system.l3cache.xbar.mem_side_ports
@@ -292,8 +313,8 @@ system.system_port = system.membus.cpu_side_ports
periodicStatDump(period)
# run Forrest, run!
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"
m5.instantiate()
m5.simulate(nxt_state * period)

156
configs/dram/low_power_sweep.py
View File

@@ -40,7 +40,7 @@ from m5.objects import *
from m5.util import addToPath
from m5.stats import periodicStatDump
addToPath('../')
addToPath("../")
from common import ObjectList
from common import MemConfig
@@ -52,46 +52,70 @@ from common import MemConfig
# through an idle state with no requests to enforce self-refresh.
parser = argparse.ArgumentParser(
formatter_class=argparse.ArgumentDefaultsHelpFormatter)
formatter_class=argparse.ArgumentDefaultsHelpFormatter
)
# Use a single-channel DDR4-2400 in 16x4 configuration by default
parser.add_argument("--mem-type", default="DDR4_2400_16x4",
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_argument(
"--mem-type",
default="DDR4_2400_16x4",
choices=ObjectList.mem_list.get_names(),
help="type of memory to use",
)
parser.add_argument("--mem-ranks", "-r", type=int, default=1,
help = "Number of ranks to iterate across")
parser.add_argument(
"--mem-ranks",
"-r",
type=int,
default=1,
help="Number of ranks to iterate across",
)
parser.add_argument("--page-policy", "-p",
choices=["close_adaptive", "open_adaptive"],
default="close_adaptive", help="controller page policy")
parser.add_argument(
"--page-policy",
"-p",
choices=["close_adaptive", "open_adaptive"],
default="close_adaptive",
help="controller page policy",
)
parser.add_argument("--itt-list", "-t", default="1 20 100",
help="a list of multipliers for the max value of itt, " \
"e.g. \"1 20 100\"")
parser.add_argument(
"--itt-list",
"-t",
default="1 20 100",
help="a list of multipliers for the max value of itt, " 'e.g. "1 20 100"',
)
parser.add_argument("--rd-perc", type=int, default=100,
help = "Percentage of read commands")
parser.add_argument(
"--rd-perc", type=int, default=100, help="Percentage of read commands"
)
parser.add_argument("--addr-map",
choices=m5.objects.AddrMap.vals,
default="RoRaBaCoCh", help = "DRAM address map policy")
parser.add_argument(
"--addr-map",
choices=m5.objects.AddrMap.vals,
default="RoRaBaCoCh",
help="DRAM address map policy",
)
parser.add_argument("--idle-end", type=int, default=50000000,
help = "time in ps of an idle period at the end ")
parser.add_argument(
"--idle-end",
type=int,
default=50000000,
help="time in ps of an idle period at the end ",
)
args = parser.parse_args()
# Start with the system itself, using a multi-layer 2.0 GHz
# crossbar, delivering 64 bytes / 3 cycles (one header cycle)
# which amounts to 42.7 GByte/s per layer and thus per port.
system = System(membus = IOXBar(width = 32))
system.clk_domain = SrcClockDomain(clock = '2.0GHz',
voltage_domain =
VoltageDomain(voltage = '1V'))
system = System(membus=IOXBar(width=32))
system.clk_domain = SrcClockDomain(
clock="2.0GHz", voltage_domain=VoltageDomain(voltage="1V")
)
# We are fine with 256 MB memory for now.
mem_range = AddrRange('256MB')
mem_range = AddrRange("256MB")
# Start address is 0
system.mem_ranges = [mem_range]
@@ -130,20 +154,27 @@ period = 250000000
# We specify the states in a config file input to the traffic generator.
cfg_file_name = "lowp_sweep.cfg"
cfg_file_path = os.path.dirname(__file__) + "/" +cfg_file_name
cfg_file = open(cfg_file_path, 'w')
cfg_file_path = os.path.dirname(__file__) + "/" + cfg_file_name
cfg_file = open(cfg_file_path, "w")
# Get the number of banks
nbr_banks = int(system.mem_ctrls[0].dram.banks_per_rank.value)
# determine the burst size in bytes
burst_size = int((system.mem_ctrls[0].dram.devices_per_rank.value *
system.mem_ctrls[0].dram.device_bus_width.value *
system.mem_ctrls[0].dram.burst_length.value) / 8)
burst_size = int(
(
system.mem_ctrls[0].dram.devices_per_rank.value
* system.mem_ctrls[0].dram.device_bus_width.value
* system.mem_ctrls[0].dram.burst_length.value
)
/ 8
)
# next, get the page size in bytes (the rowbuffer size is already in bytes)
page_size = system.mem_ctrls[0].dram.devices_per_rank.value * \
system.mem_ctrls[0].dram.device_rowbuffer_size.value
page_size = (
system.mem_ctrls[0].dram.devices_per_rank.value
* system.mem_ctrls[0].dram.device_rowbuffer_size.value
)
# Inter-request delay should be such that we can hit as many transitions
# to/from low power states as possible to. We provide a min and max itt to the
@@ -151,23 +182,25 @@ page_size = system.mem_ctrls[0].dram.devices_per_rank.value * \
# seconds and we need it in ticks (ps).
itt_min = system.mem_ctrls[0].dram.tBURST.value * 1000000000000
#The itt value when set to (tRAS + tRP + tCK) covers the case where
# The itt value when set to (tRAS + tRP + tCK) covers the case where
# a read command is delayed beyond the delay from ACT to PRE_PDN entry of the
# previous command. For write command followed by precharge, this delay
# between a write and power down entry will be tRCD + tCL + tWR + tRP + tCK.
# As we use this delay as a unit and create multiples of it as bigger delays
# for the sweep, this parameter works for reads, writes and mix of them.
pd_entry_time = (system.mem_ctrls[0].dram.tRAS.value +
system.mem_ctrls[0].dram.tRP.value +
system.mem_ctrls[0].dram.tCK.value) * 1000000000000
pd_entry_time = (
system.mem_ctrls[0].dram.tRAS.value
+ system.mem_ctrls[0].dram.tRP.value
+ system.mem_ctrls[0].dram.tCK.value
) * 1000000000000
# We sweep itt max using the multipliers specified by the user.
itt_max_str = args.itt_list.strip().split()
itt_max_multiples = [ int(x) for x in itt_max_str ]
itt_max_multiples = [int(x) for x in itt_max_str]
if len(itt_max_multiples) == 0:
fatal("String for itt-max-list detected empty\n")
itt_max_values = [ pd_entry_time * m for m in itt_max_multiples ]
itt_max_values = [pd_entry_time * m for m in itt_max_multiples]
# Generate request addresses in the entire range, assume we start at 0
max_addr = mem_range.end
@@ -180,12 +213,14 @@ stride_values = [burst_size, mid_stride, max_stride]
# be selective about bank utilization instead of going from 1 to the number of
# banks
bank_util_values = [1, int(nbr_banks/2), nbr_banks]
bank_util_values = [1, int(nbr_banks / 2), nbr_banks]
# Next we create the config file, but first a comment
cfg_file.write("""# STATE state# period mode=DRAM
cfg_file.write(
"""# STATE state# period mode=DRAM
# read_percent start_addr end_addr req_size min_itt max_itt data_limit
# stride_size page_size #banks #banks_util addr_map #ranks\n""")
# stride_size page_size #banks #banks_util addr_map #ranks\n"""
)
addr_map = m5.objects.AddrMap.map[args.addr_map]
@@ -193,12 +228,27 @@ nxt_state = 0
for itt_max in itt_max_values:
for bank in bank_util_values:
for stride_size in stride_values:
cfg_file.write("STATE %d %d %s %d 0 %d %d "
"%d %d %d %d %d %d %d %d %d\n" %
(nxt_state, period, "DRAM", args.rd_perc, max_addr,
burst_size, itt_min, itt_max, 0, stride_size,
page_size, nbr_banks, bank, addr_map,
args.mem_ranks))
cfg_file.write(
"STATE %d %d %s %d 0 %d %d "
"%d %d %d %d %d %d %d %d %d\n"
% (
nxt_state,
period,
"DRAM",
args.rd_perc,
max_addr,
burst_size,
itt_min,
itt_max,
0,
stride_size,
page_size,
nbr_banks,
bank,
addr_map,
args.mem_ranks,
)
)
nxt_state = nxt_state + 1
# State for idle period
@@ -217,7 +267,7 @@ cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state, nxt_state))
cfg_file.close()
# create a traffic generator, and point it to the file we just created
system.tgen = TrafficGen(config_file = cfg_file_path)
system.tgen = TrafficGen(config_file=cfg_file_path)
# add a communication monitor
system.monitor = CommMonitor()
@@ -232,8 +282,8 @@ system.system_port = system.membus.cpu_side_ports
# every period, dump and reset all stats
periodicStatDump(period)
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"
m5.instantiate()
@@ -242,8 +292,10 @@ m5.instantiate()
m5.simulate(nxt_state * period + idle_period)
print("--- Done DRAM low power sweep ---")
print("Fixed params - ")
print("\tburst: %d, banks: %d, max stride: %d, itt min: %s ns" % \
(burst_size, nbr_banks, max_stride, itt_min))
print(
"\tburst: %d, banks: %d, max stride: %d, itt min: %s ns"
% (burst_size, nbr_banks, max_stride, itt_min)
)
print("Swept params - ")
print("\titt max multiples input:", itt_max_multiples)
print("\titt max values", itt_max_values)

120
configs/dram/sweep.py
View File

@@ -41,7 +41,7 @@ from m5.objects import *
from m5.util import addToPath
from m5.stats import periodicStatDump
addToPath('../')
addToPath("../")
from common import ObjectList
from common import MemConfig
@@ -54,29 +54,44 @@ from common import MemConfig
parser = argparse.ArgumentParser()
dram_generators = {
"DRAM" : lambda x: x.createDram,
"DRAM_ROTATE" : lambda x: x.createDramRot,
"DRAM": lambda x: x.createDram,
"DRAM_ROTATE": lambda x: x.createDramRot,
}
# Use a single-channel DDR3-1600 x64 (8x8 topology) by default
parser.add_argument("--mem-type", default="DDR3_1600_8x8",
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_argument(
"--mem-type",
default="DDR3_1600_8x8",
choices=ObjectList.mem_list.get_names(),
help="type of memory to use",
)
parser.add_argument("--mem-ranks", "-r", type=int, default=1,
help = "Number of ranks to iterate across")
parser.add_argument(
"--mem-ranks",
"-r",
type=int,
default=1,
help="Number of ranks to iterate across",
)
parser.add_argument("--rd_perc", type=int, default=100,
help = "Percentage of read commands")
parser.add_argument(
"--rd_perc", type=int, default=100, help="Percentage of read commands"
)
parser.add_argument("--mode", default="DRAM",
choices=list(dram_generators.keys()),
help = "DRAM: Random traffic; \
DRAM_ROTATE: Traffic rotating across banks and ranks")
parser.add_argument(
"--mode",
default="DRAM",
choices=list(dram_generators.keys()),
help="DRAM: Random traffic; \
DRAM_ROTATE: Traffic rotating across banks and ranks",
)
parser.add_argument("--addr-map",
choices=ObjectList.dram_addr_map_list.get_names(),
default="RoRaBaCoCh", help = "DRAM address map policy")
parser.add_argument(
"--addr-map",
choices=ObjectList.dram_addr_map_list.get_names(),
default="RoRaBaCoCh",
help="DRAM address map policy",
)
args = parser.parse_args()
@@ -86,13 +101,13 @@ args = parser.parse_args()
# start with the system itself, using a multi-layer 2.0 GHz
# crossbar, delivering 64 bytes / 3 cycles (one header cycle)
# which amounts to 42.7 GByte/s per layer and thus per port
system = System(membus = IOXBar(width = 32))
system.clk_domain = SrcClockDomain(clock = '2.0GHz',
voltage_domain =
VoltageDomain(voltage = '1V'))
system = System(membus=IOXBar(width=32))
system.clk_domain = SrcClockDomain(
clock="2.0GHz", voltage_domain=VoltageDomain(voltage="1V")
)
# we are fine with 256 MB memory for now
mem_range = AddrRange('256MB')
mem_range = AddrRange("256MB")
system.mem_ranges = [mem_range]
# do not worry about reserving space for the backing store
@@ -131,18 +146,31 @@ period = 250000000
nbr_banks = system.mem_ctrls[0].dram.banks_per_rank.value
# determine the burst length in bytes
burst_size = int((system.mem_ctrls[0].dram.devices_per_rank.value *
system.mem_ctrls[0].dram.device_bus_width.value *
system.mem_ctrls[0].dram.burst_length.value) / 8)
burst_size = int(
(
system.mem_ctrls[0].dram.devices_per_rank.value
* system.mem_ctrls[0].dram.device_bus_width.value
* system.mem_ctrls[0].dram.burst_length.value
)
/ 8
)
# next, get the page size in bytes
page_size = system.mem_ctrls[0].dram.devices_per_rank.value * \
system.mem_ctrls[0].dram.device_rowbuffer_size.value
page_size = (
system.mem_ctrls[0].dram.devices_per_rank.value
* system.mem_ctrls[0].dram.device_rowbuffer_size.value
)
# match the maximum bandwidth of the memory, the parameter is in seconds
# and we need it in ticks (ps)
itt = getattr(system.mem_ctrls[0].dram.tBURST_MIN, 'value',
system.mem_ctrls[0].dram.tBURST.value) * 1000000000000
itt = (
getattr(
system.mem_ctrls[0].dram.tBURST_MIN,
"value",
system.mem_ctrls[0].dram.tBURST.value,
)
* 1000000000000
)
# assume we start at 0
max_addr = mem_range.end
@@ -168,27 +196,43 @@ system.system_port = system.membus.cpu_side_ports
periodicStatDump(period)
# run Forrest, run!
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"
m5.instantiate()
def trace():
addr_map = ObjectList.dram_addr_map_list.get(args.addr_map)
generator = dram_generators[args.mode](system.tgen)
for stride_size in range(burst_size, max_stride + 1, burst_size):
for bank in range(1, nbr_banks + 1):
num_seq_pkts = int(math.ceil(float(stride_size) / burst_size))
yield generator(period,
0, max_addr, burst_size, int(itt), int(itt),
args.rd_perc, 0,
num_seq_pkts, page_size, nbr_banks, bank,
addr_map, args.mem_ranks)
yield generator(
period,
0,
max_addr,
burst_size,
int(itt),
int(itt),
args.rd_perc,
0,
num_seq_pkts,
page_size,
nbr_banks,
bank,
addr_map,
args.mem_ranks,
)
yield system.tgen.createExit(0)
system.tgen.start(trace())
m5.simulate()
print("DRAM sweep with burst: %d, banks: %d, max stride: %d, request \
generation period: %d" % (burst_size, nbr_banks, max_stride, itt))
print(
"DRAM sweep with burst: %d, banks: %d, max stride: %d, request \
generation period: %d"
% (burst_size, nbr_banks, max_stride, itt)
)