python: Apply Black formatter to Python files
The command executed was `black src configs tests util`. Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
committed by
Giacomo Travaglini
Giacomo Travaglini
parent
1cfaa8da83
commit
787204c92d
@@ -45,6 +45,7 @@ from m5.objects import *
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from common.Caches import *
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from common import ObjectList
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def _get_hwp(hwp_option):
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if hwp_option == None:
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return NULL
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@@ -52,23 +53,25 @@ def _get_hwp(hwp_option):
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hwpClass = ObjectList.hwp_list.get(hwp_option)
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return hwpClass()
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def _get_cache_opts(level, options):
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opts = {}
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size_attr = '{}_size'.format(level)
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size_attr = "{}_size".format(level)
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if hasattr(options, size_attr):
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opts['size'] = getattr(options, size_attr)
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opts["size"] = getattr(options, size_attr)
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assoc_attr = '{}_assoc'.format(level)
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assoc_attr = "{}_assoc".format(level)
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if hasattr(options, assoc_attr):
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opts['assoc'] = getattr(options, assoc_attr)
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opts["assoc"] = getattr(options, assoc_attr)
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prefetcher_attr = '{}_hwp_type'.format(level)
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prefetcher_attr = "{}_hwp_type".format(level)
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if hasattr(options, prefetcher_attr):
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opts['prefetcher'] = _get_hwp(getattr(options, prefetcher_attr))
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opts["prefetcher"] = _get_hwp(getattr(options, prefetcher_attr))
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return opts
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def config_cache(options, system):
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if options.external_memory_system and (options.caches or options.l2cache):
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print("External caches and internal caches are exclusive options.\n")
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@@ -84,10 +87,12 @@ def config_cache(options, system):
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print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
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sys.exit(1)
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dcache_class, icache_class, l2_cache_class, walk_cache_class = \
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core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
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core.O3_ARM_v7aL2, \
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None
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dcache_class, icache_class, l2_cache_class, walk_cache_class = (
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core.O3_ARM_v7a_DCache,
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core.O3_ARM_v7a_ICache,
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core.O3_ARM_v7aL2,
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None,
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)
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elif options.cpu_type == "HPI":
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try:
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import cores.arm.HPI as core
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@@ -95,13 +100,21 @@ def config_cache(options, system):
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print("HPI is unavailable.")
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sys.exit(1)
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dcache_class, icache_class, l2_cache_class, walk_cache_class = \
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core.HPI_DCache, core.HPI_ICache, core.HPI_L2, None
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dcache_class, icache_class, l2_cache_class, walk_cache_class = (
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core.HPI_DCache,
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core.HPI_ICache,
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core.HPI_L2,
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None,
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)
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else:
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dcache_class, icache_class, l2_cache_class, walk_cache_class = \
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L1_DCache, L1_ICache, L2Cache, None
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dcache_class, icache_class, l2_cache_class, walk_cache_class = (
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L1_DCache,
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L1_ICache,
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L2Cache,
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None,
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)
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if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
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if buildEnv["TARGET_ISA"] in ["x86", "riscv"]:
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walk_cache_class = PageTableWalkerCache
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# Set the cache line size of the system
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@@ -118,10 +131,11 @@ def config_cache(options, system):
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# Provide a clock for the L2 and the L1-to-L2 bus here as they
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# are not connected using addTwoLevelCacheHierarchy. Use the
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# same clock as the CPUs.
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system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
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**_get_cache_opts('l2', options))
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system.l2 = l2_cache_class(
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clk_domain=system.cpu_clk_domain, **_get_cache_opts("l2", options)
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)
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system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
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system.tol2bus = L2XBar(clk_domain=system.cpu_clk_domain)
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system.l2.cpu_side = system.tol2bus.mem_side_ports
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system.l2.mem_side = system.membus.cpu_side_ports
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@@ -130,8 +144,8 @@ def config_cache(options, system):
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for i in range(options.num_cpus):
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if options.caches:
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icache = icache_class(**_get_cache_opts('l1i', options))
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dcache = dcache_class(**_get_cache_opts('l1d', options))
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icache = icache_class(**_get_cache_opts("l1i", options))
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dcache = dcache_class(**_get_cache_opts("l1d", options))
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# If we have a walker cache specified, instantiate two
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# instances here
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@@ -159,8 +173,9 @@ def config_cache(options, system):
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# When connecting the caches, the clock is also inherited
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# from the CPU in question
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
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iwalkcache, dwalkcache)
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system.cpu[i].addPrivateSplitL1Caches(
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icache, dcache, iwalkcache, dwalkcache
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)
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if options.memchecker:
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# The mem_side ports of the caches haven't been connected yet.
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@@ -174,47 +189,56 @@ def config_cache(options, system):
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# on these names. For simplicity, we would advise configuring
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# it to use this naming scheme; if this isn't possible, change
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# the names below.
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if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
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if buildEnv["TARGET_ISA"] in ["x86", "arm", "riscv"]:
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system.cpu[i].addPrivateSplitL1Caches(
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ExternalCache("cpu%d.icache" % i),
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ExternalCache("cpu%d.dcache" % i),
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ExternalCache("cpu%d.itb_walker_cache" % i),
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ExternalCache("cpu%d.dtb_walker_cache" % i))
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ExternalCache("cpu%d.icache" % i),
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ExternalCache("cpu%d.dcache" % i),
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ExternalCache("cpu%d.itb_walker_cache" % i),
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ExternalCache("cpu%d.dtb_walker_cache" % i),
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)
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else:
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system.cpu[i].addPrivateSplitL1Caches(
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ExternalCache("cpu%d.icache" % i),
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ExternalCache("cpu%d.dcache" % i))
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ExternalCache("cpu%d.icache" % i),
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ExternalCache("cpu%d.dcache" % i),
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)
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system.cpu[i].createInterruptController()
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if options.l2cache:
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system.cpu[i].connectAllPorts(
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system.tol2bus.cpu_side_ports,
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system.membus.cpu_side_ports, system.membus.mem_side_ports)
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system.membus.cpu_side_ports,
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system.membus.mem_side_ports,
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)
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elif options.external_memory_system:
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system.cpu[i].connectUncachedPorts(
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system.membus.cpu_side_ports, system.membus.mem_side_ports)
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system.membus.cpu_side_ports, system.membus.mem_side_ports
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)
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else:
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system.cpu[i].connectBus(system.membus)
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return system
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# ExternalSlave provides a "port", but when that port connects to a cache,
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# the connecting CPU SimObject wants to refer to its "cpu_side".
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# The 'ExternalCache' class provides this adaptation by rewriting the name,
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# eliminating distracting changes elsewhere in the config code.
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class ExternalCache(ExternalSlave):
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def __getattr__(cls, attr):
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if (attr == "cpu_side"):
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if attr == "cpu_side":
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attr = "port"
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return super(ExternalSlave, cls).__getattr__(attr)
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def __setattr__(cls, attr, value):
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if (attr == "cpu_side"):
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if attr == "cpu_side":
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attr = "port"
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return super(ExternalSlave, cls).__setattr__(attr, value)
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def ExternalCacheFactory(port_type):
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def make(name):
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return ExternalCache(port_data=name, port_type=port_type,
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addr_ranges=[AllMemory])
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return ExternalCache(
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port_data=name, port_type=port_type, addr_ranges=[AllMemory]
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)
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return make
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