Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5

--HG-- extra : convert_revision : 9eed6f31249ff099464044b32b882b3cc041b57a
2005-03-14 15:38:26 -05:00
parent c1f5b983f0 bc2923f78d
commit 76e6dd01ae
10 changed files with 226 additions and 133 deletions
--- a/python/m5/objects/BaseCPU.mpy
+++ b/python/m5/objects/BaseCPU.mpy
@@ -4,7 +4,7 @@ simobj BaseCPU(SimObject):
    icache = Param.BaseMem(NULL, "L1 instruction cache object")
    dcache = Param.BaseMem(NULL, "L1 data cache object")

-    if env.get('FULL_SYSTEM', 'False'):
+    if build_env['FULL_SYSTEM']:
        dtb = Param.AlphaDTB("Data TLB")
        itb = Param.AlphaITB("Instruction TLB")
        mem = Param.FunctionalMemory("memory")