diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 40a3a04b90..3da9bdadcb 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009, 2012-2013, 2015-2022 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2015-2023 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -96,6 +96,8 @@ class ArmExtension(ScopedEnum):
         "FEAT_RNG",
         "FEAT_RNG_TRAP",
         "FEAT_EVT",
+        # Armv8.6
+        "FEAT_FGT",
         # Armv8.7
         "FEAT_HCX",
         # Armv9.2
@@ -186,6 +188,8 @@ class ArmDefaultRelease(Armv8):
         # Armv8.5
         "FEAT_FLAGM2",
         "FEAT_EVT",
+        # Armv8.6
+        "FEAT_FGT",
         # Armv8.7
         "FEAT_HCX",
         # Armv9.2
@@ -239,8 +243,14 @@ class Armv85(Armv84):
     ]
 
 
-class Armv87(Armv85):
+class Armv86(Armv85):
     extensions = Armv85.extensions + [
+        "FEAT_FGT",
+    ]
+
+
+class Armv87(Armv86):
+    extensions = Armv86.extensions + [
         "FEAT_HCX",
     ]
 
diff --git a/src/arch/arm/isa/insts/branch64.isa b/src/arch/arm/isa/insts/branch64.isa
index f437651af3..73ab70b5f1 100644
--- a/src/arch/arm/isa/insts/branch64.isa
+++ b/src/arch/arm/isa/insts/branch64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2013, 2016, 2018, 2020 ARM Limited
+// Copyright (c) 2011-2013, 2016, 2018, 2020, 2023 Arm Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -200,11 +200,19 @@ let {{
                         HtmFailureFaultCause::EXCEPTION);
                     return fault;
                 }
+
                 Addr newPc;
                 CPSR cpsr = Cpsr;
                 CPSR spsr = Spsr;
 
                 ExceptionLevel curr_el = currEL(cpsr);
+
+                if (fgtEnabled(xc->tcBase()) && curr_el == EL1 &&
+                    static_cast<HFGITR>(xc->tcBase()->readMiscReg(MISCREG_HFGITR_EL2)).eret) {
+                    return std::make_shared<HypervisorTrap>(
+                        machInst, %(trap_iss)d, ExceptionClass::TRAPPED_ERET);
+                }
+
                 switch (curr_el) {
                   case EL3:
                     newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL3);
@@ -268,7 +276,7 @@ let {{
     '''
     instFlags = ['IsSerializeAfter', 'IsNonSpeculative', 'IsSquashAfter']
     bIop = ArmInstObjParams('eret', 'Eret64', "BranchEret64",
-                            bCode%{'op': ''}, instFlags)
+                            bCode%{'op': '', 'trap_iss' : 0b00}, instFlags)
     header_output += BasicDeclare.subst(bIop)
     decoder_output += BasicConstructor64.subst(bIop)
     exec_output += BasicExecute.subst(bIop)
@@ -278,7 +286,8 @@ let {{
                 fault = authIA(xc->tcBase(), newPc, XOp1, &newPc);
                 '''
     bIop = ArmInstObjParams('eretaa', 'Eretaa', "BranchEretA64",
-                            bCode % {'op': pac_code} , instFlags)
+                            bCode % {'op': pac_code, 'trap_iss' : 0b10},
+                            instFlags)
     header_output  += BasicDeclare.subst(bIop)
     decoder_output += BasicConstructor64.subst(bIop)
     exec_output    += BasicExecute.subst(bIop)
@@ -288,7 +297,8 @@ let {{
                 fault = authIB(xc->tcBase(), newPc, XOp1, &newPc);
                 '''
     bIop = ArmInstObjParams('eretab', 'Eretab', "BranchEretA64",
-                            bCode % {'op': pac_code} , instFlags)
+                            bCode % {'op': pac_code, 'trap_iss' : 0b11},
+                            instFlags)
     header_output += BasicDeclare.subst(bIop)
     decoder_output += BasicConstructor64.subst(bIop)
     exec_output += BasicExecute.subst(bIop)
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index a617dc3ebb..87f87130ce 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2013, 2016-2022 Arm Limited
+// Copyright (c) 2011-2013, 2016-2023 Arm Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -335,13 +335,18 @@ let {{
     decoder_output += RegMiscRegOp64Constructor.subst(mrsIop)
     exec_output += BasicExecute.subst(mrsIop)
 
-    buildDataXRegInst("mrsNZCV", 1, '''
+    mrsNZCVCode = '''
         CPSR cpsr = 0;
         cpsr.nz = CondCodesNZ;
         cpsr.c = CondCodesC;
         cpsr.v = CondCodesV;
         XDest = cpsr;
-    ''')
+    '''
+    mrsNZCViop = ArmInstObjParams("mrs", "MrsNZCV64",
+                                  "RegMiscRegImmOp64", mrsNZCVCode)
+    header_output += RegMiscRegOp64Declare.subst(mrsNZCViop)
+    decoder_output += RegMiscRegOp64Constructor.subst(mrsNZCViop)
+    exec_output += BasicExecute.subst(mrsNZCViop)
 
     msrCode = msr_check_code + '''
         MiscDest_ud = XOp1;
@@ -382,12 +387,17 @@ let {{
     exec_output += DvmInitiateAcc.subst(msrTlbiSIop)
     exec_output += DvmCompleteAcc.subst(msrTlbiSIop)
 
-    buildDataXRegInst("msrNZCV", 1, '''
+    msrNZCVCode = '''
         CPSR cpsr = XOp1;
         CondCodesNZ = cpsr.nz;
         CondCodesC = cpsr.c;
         CondCodesV = cpsr.v;
-    ''')
+    '''
+    msrNZCVIop = ArmInstObjParams("msr", "MsrNZCV64", "MiscRegRegImmOp64",
+                                  msrNZCVCode)
+    header_output += MiscRegRegOp64Declare.subst(msrNZCVIop)
+    decoder_output += MiscRegRegOp64Constructor.subst(msrNZCVIop)
+    exec_output += BasicExecute.subst(msrNZCVIop)
 
 
     msrdczva_ea_code = msr_check_code
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index bfcb69340d..86e9e8943c 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2010-2013,2017-2021 Arm Limited
+// Copyright (c) 2010-2013,2017-2021,2023 Arm Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -40,6 +40,13 @@ let {{
     svcCode = '''
     ThreadContext *tc = xc->tcBase();
 
+    if (fgtEnabled(tc) && currEL(tc) == EL0 && !ELIsInHost(tc, EL0) &&
+        ELIs64(tc, EL1) && static_cast<HFGITR>(
+            tc->readMiscReg(MISCREG_HFGITR_EL2)).svcEL0) {
+        return std::make_shared<HypervisorTrap>(
+            machInst, imm, ExceptionClass::SVC);
+    }
+
     bool have_semi = ArmSystem::haveSemihosting(tc);
     if (have_semi && Thumb && imm == ArmSemihosting::T32Imm) {
         // Enable gem5 extensions since we can't distinguish in thumb.
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index 46d72d21c3..5678195415 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2013, 2016-2018, 2020-2021 Arm Limited
+// Copyright (c) 2011-2013, 2016-2018, 2020-2021, 2023 Arm Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -43,7 +43,29 @@ let {{
             HtmFailureFaultCause::EXCEPTION);
         return fault;
     }
-    fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5));
+
+    const uint32_t iss = bits(machInst, 20, 5);
+    if (fgtEnabled(xc->tcBase())) {
+        ExceptionLevel curr_el = currEL(xc->tcBase());
+        HFGITR hfgitr = xc->tcBase()->readMiscReg(MISCREG_HFGITR_EL2);
+        switch (curr_el) {
+          case EL0:
+            if (!ELIsInHost(xc->tcBase(), curr_el) && hfgitr.svcEL0) {
+                return std::make_shared<HypervisorTrap>(
+                    machInst, iss, ExceptionClass::SVC_64);
+            }
+            break;
+          case EL1:
+            if (hfgitr.svcEL1) {
+                return std::make_shared<HypervisorTrap>(
+                    machInst, iss, ExceptionClass::SVC_64);
+            }
+            break;
+          default:
+            break;
+        }
+    }
+    fault = std::make_shared<SupervisorCall>(machInst, iss);
     '''
 
     svcIop = ArmInstObjParams("svc", "Svc64", "ImmOp64",
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index f1c69cc007..25993829a3 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1114,6 +1114,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 4, 1, 1, 3), MISCREG_HSTR_EL2 },
     { MiscRegNum64(3, 4, 1, 1, 4), MISCREG_HFGRTR_EL2 },
     { MiscRegNum64(3, 4, 1, 1, 5), MISCREG_HFGWTR_EL2 },
+    { MiscRegNum64(3, 4, 1, 1, 6), MISCREG_HFGITR_EL2 },
     { MiscRegNum64(3, 4, 1, 1, 7), MISCREG_HACR_EL2 },
     { MiscRegNum64(3, 4, 1, 2, 0), MISCREG_ZCR_EL2 },
     { MiscRegNum64(3, 4, 1, 2, 2), MISCREG_HCRX_EL2 },
@@ -1249,6 +1250,164 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 7, 14, 2, 2), MISCREG_CNTPS_CVAL_EL1 }
 };
 
+template <bool read>
+HFGTR
+fgtRegister(ThreadContext *tc)
+{
+    if constexpr (read) {
+        return tc->readMiscReg(MISCREG_HFGRTR_EL2);
+    } else {
+        return tc->readMiscReg(MISCREG_HFGWTR_EL2);
+    }
+}
+
+/**
+ * Template helper for fine grained traps at EL0
+ *
+ * @tparam read: is this a read access to the register?
+ * @tparam r_bitfield: register (HFGTR) bitfield
+ */
+template<bool read, auto r_bitfield>
+Fault
+faultFgtEL0(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+    const bool in_host = EL2Enabled(tc) && hcr.e2h && hcr.tge;
+    if (fgtEnabled(tc) && !in_host &&
+        fgtRegister<read>(tc).*r_bitfield) {
+        return inst.generateTrap(EL2);
+    } else {
+        return NoFault;
+    }
+}
+
+/**
+ * Template helper for fine grained traps at EL1
+ *
+ * @tparam read: is this a read access to the register?
+ * @tparam r_bitfield: register (HFGTR) bitfield
+ */
+template<bool read, auto r_bitfield>
+Fault
+faultFgtEL1(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    if (fgtEnabled(tc) && fgtRegister<read>(tc).*r_bitfield) {
+        return inst.generateTrap(EL2);
+    } else {
+        return NoFault;
+    }
+}
+
+/**
+ * Template helper for fine grained traps at EL1
+ *
+ * @tparam r_bitfield: register (HFGITR) bitfield
+ */
+template<auto r_bitfield>
+Fault
+faultFgtInstEL1(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    if (fgtEnabled(tc) &&
+        static_cast<HFGITR>(tc->readMiscReg(MISCREG_HFGITR_EL2)).*r_bitfield) {
+        return inst.generateTrap(EL2);
+    } else {
+        return NoFault;
+    }
+}
+
+/**
+ * Template helper for fine grained traps at EL1
+ *
+ * @tparam g_bitfield: group (HCR) bitfield
+ */
+template <auto g_bitfield>
+Fault
+faultHcrEL1(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+    if (EL2Enabled(tc) && hcr.*g_bitfield) {
+        return inst.generateTrap(EL2);
+    } else {
+        return NoFault;
+    }
+}
+
+/**
+ * Template helper for fine grained traps at EL0
+ *
+ * @tparam read: is this a read access to the register?
+ * @tparam g_bitfield: group (HCR) bitfield
+ * @tparam r_bitfield: register (HFGTR) bitfield
+ */
+template<bool read, auto g_bitfield, auto r_bitfield>
+Fault
+faultHcrFgtEL0(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+    const bool in_host = EL2Enabled(tc) && hcr.e2h && hcr.tge;
+
+    if (EL2Enabled(tc) && !in_host && hcr.*g_bitfield) {
+        return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtEL0<read, r_bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
+    } else {
+        return NoFault;
+    }
+}
+
+/**
+ * Template helper for fine grained traps at EL1
+ *
+ * @tparam read: is this a read access to the register?
+ * @tparam g_bitfield: group (HCR) bitfield
+ * @tparam r_bitfield: register (HFGTR) bitfield
+ */
+template<bool read, auto g_bitfield, auto r_bitfield>
+Fault
+faultHcrFgtEL1(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+
+    if (EL2Enabled(tc) && hcr.*g_bitfield) {
+        return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtEL1<read, r_bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
+    } else {
+        return NoFault;
+    }
+}
+
+/**
+ * Template helper for fine grained traps at EL1
+ *
+ * @tparam g_bitfield: group (HCR) bitfield
+ * @tparam r_bitfield: register (HFGITR) bitfield
+ */
+template<auto g_bitfield, auto r_bitfield>
+Fault
+faultHcrFgtInstEL1(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+
+    if (EL2Enabled(tc) && hcr.*g_bitfield) {
+        return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtInstEL1<r_bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
+    } else {
+        return NoFault;
+    }
+}
+
 Fault
 faultSpEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
            const MiscRegOp64 &inst)
@@ -1455,6 +1614,7 @@ faultPouEL0(const MiscRegLUTEntry &entry,
     }
 }
 
+template <auto bitfield>
 Fault
 faultPouEL1(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
@@ -1466,11 +1626,15 @@ faultPouEL1(const MiscRegLUTEntry &entry,
     } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
                hcr.tocu) {
         return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtInstEL1<bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
     } else {
         return NoFault;
     }
 }
 
+template <auto bitfield>
 Fault
 faultPouIsEL1(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
@@ -1482,6 +1646,9 @@ faultPouIsEL1(const MiscRegLUTEntry &entry,
     } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
                hcr.ticab) {
         return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtInstEL1<bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
     } else {
         return NoFault;
     }
@@ -1503,8 +1670,10 @@ faultCtrEL0(const MiscRegLUTEntry &entry,
          } else {
             return inst.generateTrap(EL1);
          }
-     } else if (el2_enabled && !in_host && hcr.tid2) {
-        return inst.generateTrap(EL2);
+     } else if (auto fault = faultHcrFgtEL0<
+                    true, &HCR::tid2, &HFGTR::ctrEL0>(entry, tc, inst);
+                fault != NoFault) {
+        return fault;
      } else if (el2_enabled && in_host && !sctlr2.uct) {
         return inst.generateTrap(EL2);
      } else {
@@ -1714,14 +1883,20 @@ faultIccSgiEL2(const MiscRegLUTEntry &entry,
     }
 }
 
+template<bool read, auto r_bitfield>
 Fault
 faultCpacrEL1(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
 {
     const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
     const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
-    if (EL2Enabled(tc) && cptr_el2.tcpac) {
+
+    const bool el2_enabled = EL2Enabled(tc);
+    if (el2_enabled && cptr_el2.tcpac) {
         return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtEL1<read, r_bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
     } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
         return inst.generateTrap(EL3);
     } else {
@@ -1753,17 +1928,7 @@ faultCpacrVheEL2(const MiscRegLUTEntry &entry,
     }
 }
 
-#define HCR_TRAP(bitfield) [] (const MiscRegLUTEntry &entry, \
-    ThreadContext *tc, const MiscRegOp64 &inst) -> Fault     \
-{                                                            \
-    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);        \
-    if (EL2Enabled(tc) && hcr.bitfield) {                    \
-        return inst.generateTrap(EL2);                       \
-    } else {                                                 \
-        return NoFault;                                      \
-    }                                                        \
-}
-
+template <auto bitfield>
 Fault
 faultTlbiOsEL1(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
@@ -1775,11 +1940,15 @@ faultTlbiOsEL1(const MiscRegLUTEntry &entry,
     } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
                hcr.ttlbos) {
         return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtInstEL1<bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
     } else {
         return NoFault;
     }
 }
 
+template <auto bitfield>
 Fault
 faultTlbiIsEL1(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
@@ -1791,11 +1960,15 @@ faultTlbiIsEL1(const MiscRegLUTEntry &entry,
     } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
                hcr.ttlbis) {
         return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtInstEL1<bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
     } else {
         return NoFault;
     }
 }
 
+template <bool read, auto r_bitfield>
 Fault
 faultCacheEL1(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
@@ -1807,19 +1980,28 @@ faultCacheEL1(const MiscRegLUTEntry &entry,
     } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
                hcr.tid4) {
         return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtEL1<read, r_bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
     } else {
         return NoFault;
     }
 }
 
+template <bool read, auto r_bitfield>
 Fault
 faultPauthEL1(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
 {
     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
-    if (EL2Enabled(tc) && !hcr.apk) {
+    const bool el2_enabled = EL2Enabled(tc);
+
+    if (el2_enabled && !hcr.apk) {
         return inst.generateTrap(EL2);
+    } else if (auto fault = faultFgtEL1<read, r_bitfield>(entry, tc, inst);
+               fault != NoFault) {
+        return fault;
     } else if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
         return inst.generateTrap(EL3);
     } else {
@@ -2140,6 +2322,22 @@ faultRng(const MiscRegLUTEntry &entry,
     }
 }
 
+Fault
+faultFgtCtrlRegs(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    if (HaveExt(tc, ArmExtension::FEAT_FGT)) {
+        const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+        if (ArmSystem::haveEL(tc, EL3) && !scr.fgten) {
+            return inst.generateTrap(EL3);
+        } else {
+            return NoFault;
+        }
+    } else {
+        return inst.undefined();
+    }
+}
+
 Fault
 faultIdst(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
@@ -3908,108 +4106,110 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_MIDR_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
+      .faultRead(EL1, faultFgtEL1<true, &HFGTR::midrEL1>)
       .mapsTo(MISCREG_MIDR);
     InitReg(MISCREG_MPIDR_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
+      .faultRead(EL1, faultFgtEL1<true, &HFGTR::mpidrEL1>)
       .mapsTo(MISCREG_MPIDR);
     InitReg(MISCREG_REVIDR_EL1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid1))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::tid1, &HFGTR::revidrEL1>)
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_ID_PFR0_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_PFR0);
     InitReg(MISCREG_ID_PFR1_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_PFR1);
     InitReg(MISCREG_ID_DFR0_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_DFR0);
     InitReg(MISCREG_ID_AFR0_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_AFR0);
     InitReg(MISCREG_ID_MMFR0_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_MMFR0);
     InitReg(MISCREG_ID_MMFR1_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_MMFR1);
     InitReg(MISCREG_ID_MMFR2_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_MMFR2);
     InitReg(MISCREG_ID_MMFR3_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_MMFR3);
     InitReg(MISCREG_ID_MMFR4_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_MMFR4);
     InitReg(MISCREG_ID_ISAR0_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_ISAR0);
     InitReg(MISCREG_ID_ISAR1_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_ISAR1);
     InitReg(MISCREG_ID_ISAR2_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_ISAR2);
     InitReg(MISCREG_ID_ISAR3_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_ISAR3);
     InitReg(MISCREG_ID_ISAR4_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_ISAR4);
     InitReg(MISCREG_ID_ISAR5_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_ISAR5);
     InitReg(MISCREG_ID_ISAR6_EL1)
       .allPrivileges().exceptUserMode().writes(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .mapsTo(MISCREG_ID_ISAR6);
     InitReg(MISCREG_MVFR0_EL1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().exceptUserMode().writes(0)
       .mapsTo(MISCREG_MVFR0);
     InitReg(MISCREG_MVFR1_EL1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().exceptUserMode().writes(0)
       .mapsTo(MISCREG_MVFR1);
     InitReg(MISCREG_MVFR2_EL1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_ID_AA64PFR0_EL1)
       .reset([this,release=release,tc=tc](){
@@ -4025,14 +4225,14 @@ ISA::initializeMiscRegMetadata()
       }())
       .unserialize(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64PFR1_EL1)
       .reset(release->has(ArmExtension::FEAT_SME) ?
           0x1 << 24 : 0)
       .unserialize(0)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64DFR0_EL1)
       .reset([p](){
@@ -4041,22 +4241,22 @@ ISA::initializeMiscRegMetadata()
           return dfr0_el1;
       }())
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64DFR1_EL1)
       .reset(p.id_aa64dfr1_el1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64AFR0_EL1)
       .reset(p.id_aa64afr0_el1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64AFR1_EL1)
       .reset(p.id_aa64afr1_el1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64ISAR0_EL1)
       .reset([p,release=release](){
@@ -4084,7 +4284,7 @@ ISA::initializeMiscRegMetadata()
           return isar0_el1;
       }())
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64ISAR1_EL1)
       .reset([p,release=release](){
@@ -4097,7 +4297,7 @@ ISA::initializeMiscRegMetadata()
           return isar1_el1;
       }())
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64MMFR0_EL1)
       .reset([p,asidbits=haveLargeAsid64,parange=physAddrRange](){
@@ -4107,7 +4307,7 @@ ISA::initializeMiscRegMetadata()
           return mmfr0_el1;
       }())
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64MMFR1_EL1)
       .reset([p,release=release](){
@@ -4120,7 +4320,7 @@ ISA::initializeMiscRegMetadata()
           return mmfr1_el1;
       }())
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_ID_AA64MMFR2_EL1)
       .reset([p,release=release](){
@@ -4132,73 +4332,86 @@ ISA::initializeMiscRegMetadata()
           return mmfr2_el1;
       }())
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid3))
+      .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
       .allPrivileges().writes(0);
 
     InitReg(MISCREG_APDAKeyHi_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apdaKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apdaKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APDAKeyLo_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apdaKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apdaKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APDBKeyHi_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apdbKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apdbKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APDBKeyLo_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apdbKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apdbKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APGAKeyHi_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apgaKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apgaKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APGAKeyLo_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apgaKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apgaKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APIAKeyHi_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apiaKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apiaKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APIAKeyLo_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apiaKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apiaKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APIBKeyHi_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apibKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apibKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_APIBKeyLo_EL1)
-      .fault(EL1, faultPauthEL1)
+      .faultRead(EL1, faultPauthEL1<true, &HFGTR::apibKey>)
+      .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apibKey>)
       .fault(EL2, faultPauthEL2)
       .allPrivileges().exceptUserMode();
 
     InitReg(MISCREG_CCSIDR_EL1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, faultCacheEL1)
+      .faultRead(EL1, faultCacheEL1<true, &HFGTR::ccsidrEL1>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_CLIDR_EL1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, faultCacheEL1)
+      .faultRead(EL1, faultCacheEL1<true, &HFGTR::clidrEL1>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_AIDR_EL1)
       .faultRead(EL0, faultIdst)
-      .faultRead(EL1, HCR_TRAP(tid1))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::tid1, &HFGTR::aidrEL1>)
       .allPrivileges().writes(0);
     InitReg(MISCREG_CSSELR_EL1)
       .allPrivileges().exceptUserMode()
-      .fault(EL1, faultCacheEL1)
+      .faultRead(EL1, faultCacheEL1<true, &HFGTR::csselrEL1>)
+      .faultWrite(EL1, faultCacheEL1<false, &HFGTR::csselrEL1>)
       .mapsTo(MISCREG_CSSELR_NS);
     InitReg(MISCREG_CTR_EL0)
       .faultRead(EL0, faultCtrEL0)
-      .faultRead(EL1, HCR_TRAP(tid2))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::tid2, &HFGTR::ctrEL0>)
       .reads(1)
       .mapsTo(MISCREG_CTR);
     InitReg(MISCREG_DCZID_EL0)
       .reset(0x04) // DC ZVA clear 64-byte chunks
+      .faultRead(EL0, faultFgtEL0<true, &HFGTR::dczidEL0>)
+      .faultRead(EL1, faultFgtEL1<true, &HFGTR::dczidEL0>)
       .reads(1);
     InitReg(MISCREG_VPIDR_EL2)
       .hyp().mon()
@@ -4210,8 +4423,8 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_VMPIDR);
     InitReg(MISCREG_SCTLR_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::sctlrEL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::sctlrEL1>)
       .res0( 0x20440 | (EnDB   ? 0 :     0x2000)
                      | (IESB   ? 0 :   0x200000)
                      | (EnDA   ? 0 :  0x8000000)
@@ -4235,11 +4448,12 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_SCTLR_EL1);
     InitReg(MISCREG_ACTLR_EL1)
       .allPrivileges().exceptUserMode()
-      .fault(EL1, HCR_TRAP(tacr))
+      .fault(EL1, faultHcrEL1<&HCR::tacr>)
       .mapsTo(MISCREG_ACTLR_NS);
     InitReg(MISCREG_CPACR_EL1)
       .allPrivileges().exceptUserMode()
-      .fault(EL1, faultCpacrEL1)
+      .faultRead(EL1, faultCpacrEL1<true, &HFGTR::cpacrEL1>)
+      .faultWrite(EL1, faultCpacrEL1<false, &HFGTR::cpacrEL1>)
       .fault(EL2, faultCpacrEL2)
       .mapsTo(MISCREG_CPACR);
     InitReg(MISCREG_CPACR_EL12)
@@ -4302,8 +4516,8 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_SDCR);
     InitReg(MISCREG_TTBR0_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::ttbr0EL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::ttbr0EL1>)
       .mapsTo(MISCREG_TTBR0_NS);
     InitReg(MISCREG_TTBR0_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4311,8 +4525,8 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_TTBR0_EL1);
     InitReg(MISCREG_TTBR1_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::ttbr1EL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::ttbr1EL1>)
       .mapsTo(MISCREG_TTBR1_NS);
     InitReg(MISCREG_TTBR1_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4320,8 +4534,8 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_TTBR1_EL1);
     InitReg(MISCREG_TCR_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::tcrEL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::tcrEL1>)
       .mapsTo(MISCREG_TTBCR_NS);
     InitReg(MISCREG_TCR_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4424,8 +4638,8 @@ ISA::initializeMiscRegMetadata()
       .mon();
     InitReg(MISCREG_AFSR0_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::afsr0EL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::afsr0EL1>)
       .mapsTo(MISCREG_ADFSR_NS);
     InitReg(MISCREG_AFSR0_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4433,16 +4647,16 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_ADFSR_NS);
     InitReg(MISCREG_AFSR1_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::afsr1EL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::afsr1EL1>)
       .mapsTo(MISCREG_AIFSR_NS);
     InitReg(MISCREG_AFSR1_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
       .fault(EL3, defaultFaultE2H_EL3)
       .mapsTo(MISCREG_AIFSR_NS);
     InitReg(MISCREG_ESR_EL1)
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::esrEL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::esrEL1>)
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_ESR_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4472,8 +4686,8 @@ ISA::initializeMiscRegMetadata()
       .mon();
     InitReg(MISCREG_FAR_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::farEL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::farEL1>)
       .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
     InitReg(MISCREG_FAR_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4489,61 +4703,61 @@ ISA::initializeMiscRegMetadata()
       .mon();
     InitReg(MISCREG_IC_IALLUIS)
       .warnNotFail()
-      .faultWrite(EL1, faultPouIsEL1)
+      .faultWrite(EL1, faultPouIsEL1<&HFGITR::icialluis>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_PAR_EL1)
       .allPrivileges().exceptUserMode()
       .mapsTo(MISCREG_PAR_NS);
     InitReg(MISCREG_IC_IALLU)
       .warnNotFail()
-      .faultWrite(EL1, faultPouEL1)
+      .faultWrite(EL1, faultPouEL1<&HFGITR::iciallu>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_DC_IVAC_Xt)
-      .faultWrite(EL1, HCR_TRAP(tpc))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tpc, &HFGITR::dcivac>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_DC_ISW_Xt)
       .warnNotFail()
-      .faultWrite(EL1, HCR_TRAP(tsw))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tsw, &HFGITR::dcisw>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_AT_S1E1R_Xt)
-      .faultWrite(EL1, HCR_TRAP(at))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::at, &HFGITR::ats1e1r>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_AT_S1E1W_Xt)
-      .faultWrite(EL1, HCR_TRAP(at))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::at, &HFGITR::ats1e1w>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_AT_S1E0R_Xt)
-      .faultWrite(EL1, HCR_TRAP(at))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::at, &HFGITR::ats1e0r>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_AT_S1E0W_Xt)
-      .faultWrite(EL1, HCR_TRAP(at))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::at, &HFGITR::ats1e0w>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_DC_CSW_Xt)
       .warnNotFail()
-      .faultWrite(EL1, HCR_TRAP(tsw))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tsw, &HFGITR::dccsw>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_DC_CISW_Xt)
       .warnNotFail()
-      .faultWrite(EL1, HCR_TRAP(tsw))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tsw, &HFGITR::dccisw>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_DC_ZVA_Xt)
       .writes(1)
       .faultWrite(EL0, faultDczvaEL0)
-      .faultWrite(EL1, HCR_TRAP(tdz));
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tdz, &HFGITR::dczva>);
     InitReg(MISCREG_IC_IVAU_Xt)
       .faultWrite(EL0, faultPouEL0)
-      .faultWrite(EL1, faultPouEL1)
+      .faultWrite(EL1, faultPouEL1<&HFGITR::icivau>)
       .writes(1);
     InitReg(MISCREG_DC_CVAC_Xt)
       .faultWrite(EL0, faultCvacEL0)
-      .faultWrite(EL1, HCR_TRAP(tpc))
+      .faultWrite(EL1, faultHcrEL1<&HCR::tpc>)
       .writes(1);
     InitReg(MISCREG_DC_CVAU_Xt)
       .faultWrite(EL0, faultPouEL0)
-      .faultWrite(EL1, faultPouEL1)
+      .faultWrite(EL1, faultPouEL1<&HFGITR::dccvau>)
       .writes(1);
     InitReg(MISCREG_DC_CIVAC_Xt)
       .faultWrite(EL0, faultCvacEL0)
-      .faultWrite(EL1, HCR_TRAP(tpc))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tpc, &HFGITR::dccivac>)
       .writes(1);
     InitReg(MISCREG_AT_S1E2R_Xt)
       .monNonSecureWrite().hypWrite();
@@ -4562,58 +4776,58 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_AT_S1E3W_Xt)
       .monSecureWrite().monNonSecureWrite();
     InitReg(MISCREG_TLBI_VMALLE1OS)
-      .faultWrite(EL1, faultTlbiOsEL1)
+      .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivmalle1os>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAE1OS_Xt)
-      .faultWrite(EL1, faultTlbiOsEL1)
+      .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivae1os>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_ASIDE1OS_Xt)
-      .faultWrite(EL1, faultTlbiOsEL1)
+      .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbiaside1os>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAAE1OS_Xt)
-      .faultWrite(EL1, faultTlbiOsEL1)
+      .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivaae1os>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VALE1OS_Xt)
-      .faultWrite(EL1, faultTlbiOsEL1)
+      .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivale1os>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAALE1OS_Xt)
-      .faultWrite(EL1, faultTlbiOsEL1)
+      .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivaale1os>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VMALLE1IS)
-      .faultWrite(EL1, faultTlbiIsEL1)
+      .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivmalle1is>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAE1IS_Xt)
-      .faultWrite(EL1, faultTlbiIsEL1)
+      .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivae1is>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
-      .faultWrite(EL1, faultTlbiIsEL1)
+      .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbiaside1is>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAAE1IS_Xt)
-      .faultWrite(EL1, faultTlbiIsEL1)
+      .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivaae1is>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VALE1IS_Xt)
-      .faultWrite(EL1, faultTlbiIsEL1)
+      .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivale1is>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAALE1IS_Xt)
-      .faultWrite(EL1, faultTlbiIsEL1)
+      .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivaale1is>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VMALLE1)
-      .faultWrite(EL1, HCR_TRAP(ttlb))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivmalle1>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAE1_Xt)
-      .faultWrite(EL1, HCR_TRAP(ttlb))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivae1>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_ASIDE1_Xt)
-      .faultWrite(EL1, HCR_TRAP(ttlb))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbiaside1>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAAE1_Xt)
-      .faultWrite(EL1, HCR_TRAP(ttlb))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaae1>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VALE1_Xt)
-      .faultWrite(EL1, HCR_TRAP(ttlb))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivale1>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_VAALE1_Xt)
-      .faultWrite(EL1, HCR_TRAP(ttlb))
+      .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaale1>)
       .writes(1).exceptUserMode();
     InitReg(MISCREG_TLBI_IPAS2E1OS_Xt)
       .hypWrite().monSecureWrite().monNonSecureWrite();
@@ -4724,8 +4938,8 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_PMOVSSET);
     InitReg(MISCREG_MAIR_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::mairEL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::mairEL1>)
       .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
     InitReg(MISCREG_MAIR_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4733,8 +4947,8 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
     InitReg(MISCREG_AMAIR_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::amairEL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::amairEL1>)
       .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
     InitReg(MISCREG_AMAIR_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4756,6 +4970,8 @@ ISA::initializeMiscRegMetadata()
       .allPrivileges().exceptUserMode();
     InitReg(MISCREG_VBAR_EL1)
       .allPrivileges().exceptUserMode()
+      .faultRead(EL1, faultFgtEL1<true, &HFGTR::vbarEL1>)
+      .faultWrite(EL1, faultFgtEL1<false, &HFGTR::vbarEL1>)
       .mapsTo(MISCREG_VBAR_NS);
     InitReg(MISCREG_VBAR_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4785,8 +5001,8 @@ ISA::initializeMiscRegMetadata()
       .mon();
     InitReg(MISCREG_CONTEXTIDR_EL1)
       .allPrivileges().exceptUserMode()
-      .faultRead(EL1, HCR_TRAP(trvm))
-      .faultWrite(EL1, HCR_TRAP(tvm))
+      .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::contextidrEL1>)
+      .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::contextidrEL1>)
       .mapsTo(MISCREG_CONTEXTIDR_NS);
     InitReg(MISCREG_CONTEXTIDR_EL12)
       .fault(EL2, defaultFaultE2H_EL2)
@@ -4794,12 +5010,21 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_CONTEXTIDR_NS);
     InitReg(MISCREG_TPIDR_EL1)
       .allPrivileges().exceptUserMode()
+      .faultRead(EL1, faultFgtEL1<true, &HFGTR::tpidrEL1>)
+      .faultWrite(EL1, faultFgtEL1<false, &HFGTR::tpidrEL1>)
       .mapsTo(MISCREG_TPIDRPRW_NS);
     InitReg(MISCREG_TPIDR_EL0)
       .allPrivileges()
+      .faultRead(EL0, faultFgtEL0<true, &HFGTR::tpidrEL0>)
+      .faultWrite(EL0, faultFgtEL0<false, &HFGTR::tpidrEL0>)
+      .faultRead(EL1, faultFgtEL1<true, &HFGTR::tpidrEL0>)
+      .faultWrite(EL1, faultFgtEL1<false, &HFGTR::tpidrEL0>)
       .mapsTo(MISCREG_TPIDRURW_NS);
     InitReg(MISCREG_TPIDRRO_EL0)
       .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
+      .faultRead(EL0, faultFgtEL0<true, &HFGTR::tpidrroEL0>)
+      .faultRead(EL1, faultFgtEL1<true, &HFGTR::tpidrroEL0>)
+      .faultWrite(EL1, faultFgtEL1<false, &HFGTR::tpidrroEL0>)
       .mapsTo(MISCREG_TPIDRURO_NS);
     InitReg(MISCREG_TPIDR_EL2)
       .hyp().mon()
@@ -5187,9 +5412,13 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_ICC_IGRPEN0_EL1)
         .res0(0xFFFFFFFE) // [31:1]
         .allPrivileges().exceptUserMode()
+        .faultRead(EL1, faultFgtEL1<true, &HFGTR::iccIgrpEnEL1>)
+        .faultWrite(EL1, faultFgtEL1<false, &HFGTR::iccIgrpEnEL1>)
         .mapsTo(MISCREG_ICC_IGRPEN0);
     InitReg(MISCREG_ICC_IGRPEN1_EL1)
         .banked64()
+        .faultRead(EL1, faultFgtEL1<true, &HFGTR::iccIgrpEnEL1>)
+        .faultWrite(EL1, faultFgtEL1<false, &HFGTR::iccIgrpEnEL1>)
         .mapsTo(MISCREG_ICC_IGRPEN1);
     InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
         .bankedChild()
@@ -5502,7 +5731,7 @@ ISA::initializeMiscRegMetadata()
             return zfr0_el1;
         }())
         .faultRead(EL0, faultIdst)
-        .faultRead(EL1, HCR_TRAP(tid3))
+        .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
         .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_ZCR_EL3)
         .reset(sveVL - 1)
@@ -5542,7 +5771,7 @@ ISA::initializeMiscRegMetadata()
             return smfr0_el1;
         }())
         .faultRead(EL0, faultIdst)
-        .faultRead(EL1, HCR_TRAP(tid3))
+        .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
         .allPrivileges().writes(0);
     InitReg(MISCREG_SVCR)
         .res0([](){
@@ -5565,7 +5794,7 @@ ISA::initializeMiscRegMetadata()
             return smidr_el1;
         }())
         .faultRead(EL0, faultIdst)
-        .faultRead(EL1, HCR_TRAP(tid1))
+        .faultRead(EL1, faultHcrEL1<&HCR::tid1>)
         .allPrivileges().writes(0);
     InitReg(MISCREG_SMPRI_EL1)
         .res0(mask(63, 4))
@@ -5644,6 +5873,17 @@ ISA::initializeMiscRegMetadata()
         .unverifiable()
         .allPrivileges().writes(0);
 
+    // FEAT_FGT extension
+    InitReg(MISCREG_HFGRTR_EL2)
+      .fault(EL2, faultFgtCtrlRegs)
+      .hyp().mon(release->has(ArmExtension::FEAT_FGT));
+    InitReg(MISCREG_HFGWTR_EL2)
+      .fault(EL2, faultFgtCtrlRegs)
+      .hyp().mon(release->has(ArmExtension::FEAT_FGT));
+    InitReg(MISCREG_HFGITR_EL2)
+      .fault(EL2, faultFgtCtrlRegs)
+      .hyp().mon(release->has(ArmExtension::FEAT_FGT));
+
     // Dummy registers
     InitReg(MISCREG_NOP)
       .allPrivileges();
@@ -5691,14 +5931,6 @@ ISA::initializeMiscRegMetadata()
       .warnNotFail()
       .fault(faultUnimplemented);
 
-    // FGT extension (unimplemented)
-    InitReg(MISCREG_HFGRTR_EL2)
-      .unimplemented()
-      .warnNotFail();
-    InitReg(MISCREG_HFGWTR_EL2)
-      .unimplemented()
-      .warnNotFail();
-
     // Register mappings for some unimplemented registers:
     // ESR_EL1 -> DFSR
     // RMR_EL1 -> RMR
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index cb03841848..2077040e57 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1096,6 +1096,11 @@ namespace ArmISA
         MISCREG_RNDR,
         MISCREG_RNDRRS,
 
+        // FEAT_FGT
+        MISCREG_HFGITR_EL2,
+        MISCREG_HFGRTR_EL2,
+        MISCREG_HFGWTR_EL2,
+
         // NUM_PHYS_MISCREGS specifies the number of actual physical
         // registers, not considering the following pseudo-registers
         // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
@@ -1126,10 +1131,6 @@ namespace ArmISA
         MISCREG_VSESR_EL2,
         MISCREG_VDISR_EL2,
 
-        // FGT extension (unimplemented)
-        MISCREG_HFGRTR_EL2,
-        MISCREG_HFGWTR_EL2,
-
         // PSTATE
         MISCREG_PAN,
         MISCREG_UAO,
@@ -2766,6 +2767,10 @@ namespace ArmISA
         "rndr",
         "rndrrs",
 
+        "hfgitr_el2",
+        "hfgrtr_el2",
+        "hfgwtr_el2",
+
         "num_phys_regs",
 
         // Dummy registers
@@ -2784,8 +2789,6 @@ namespace ArmISA
         "disr_el1",
         "vsesr_el2",
         "vdisr_el2",
-        "hfgrtr_el2",
-        "hfgwtr_el2",
 
         // PSTATE
         "pan",
diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh
index 00640dd339..f9a16c297a 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2022 Arm Limited
+ * Copyright (c) 2010-2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -363,6 +363,7 @@ namespace ArmISA
     BitUnion64(SCR)
         Bitfield<40> trndr;
         Bitfield<38> hxen;
+        Bitfield<27> fgten;
         Bitfield<21> fien;
         Bitfield<20> nmea;
         Bitfield<19> ease;
@@ -931,6 +932,117 @@ namespace ArmISA
         Bitfield<3,0>   pcsample;
    EndBitUnion(DEVID)
 
+    BitUnion64(HFGITR)
+        Bitfield<54> dccvac;
+        Bitfield<53> svcEL1;
+        Bitfield<52> svcEL0;
+        Bitfield<51> eret;
+        Bitfield<47> tlbivaale1;
+        Bitfield<46> tlbivale1;
+        Bitfield<45> tlbivaae1;
+        Bitfield<44> tlbiaside1;
+        Bitfield<43> tlbivae1;
+        Bitfield<42> tlbivmalle1;
+        Bitfield<41> tlbirvaale1;
+        Bitfield<40> tlbirvale1;
+        Bitfield<39> tlbirvaae1;
+        Bitfield<38> tlbirvae1;
+        Bitfield<37> tlbirvaale1is;
+        Bitfield<36> tlbirvale1is;
+        Bitfield<35> tlbirvaae1is;
+        Bitfield<34> tlbirvae1is;
+        Bitfield<33> tlbivaale1is;
+        Bitfield<32> tlbivale1is;
+        Bitfield<31> tlbivaae1is;
+        Bitfield<30> tlbiaside1is;
+        Bitfield<29> tlbivae1is;
+        Bitfield<28> tlbivmalle1is;
+        Bitfield<27> tlbirvaale1os;
+        Bitfield<26> tlbirvale1os;
+        Bitfield<25> tlbirvaae1os;
+        Bitfield<24> tlbirvae1os;
+        Bitfield<23> tlbivaale1os;
+        Bitfield<22> tlbivale1os;
+        Bitfield<21> tlbivaae1os;
+        Bitfield<20> tlbiaside1os;
+        Bitfield<19> tlbivae1os;
+        Bitfield<18> tlbivmalle1os;
+        Bitfield<17> ats1e1wp;
+        Bitfield<16> ats1e1rp;
+        Bitfield<15> ats1e0w;
+        Bitfield<14> ats1e0r;
+        Bitfield<13> ats1e1w;
+        Bitfield<12> ats1e1r;
+        Bitfield<11> dczva;
+        Bitfield<10> dccivac;
+        Bitfield<9> dccvapd;
+        Bitfield<8> dccvap;
+        Bitfield<7> dccvau;
+        Bitfield<6> dccisw;
+        Bitfield<5> dccsw;
+        Bitfield<4> dcisw;
+        Bitfield<3> dcivac;
+        Bitfield<2> icivau;
+        Bitfield<1> iciallu;
+        Bitfield<0> icialluis;
+    EndBitUnion(HFGITR)
+
+    // HFGRTR and HFGWTR. Some fields are
+    // for HFGRTR only (RO registers)
+    BitUnion64(HFGTR)
+        Bitfield<50> nAccdataEL1;
+        Bitfield<49> erxaddrEL1;
+        Bitfield<48> erxpfgcdnEL1;
+        Bitfield<47> erxpfgctlEL1;
+        Bitfield<46> erxpfgfEL1; // RES0 for HFGWTR
+        Bitfield<45> erxmiscNEL1;
+        Bitfield<44> erxstatusEL1;
+        Bitfield<43> erxctlrEL1;
+        Bitfield<42> erxfrEL1;
+        Bitfield<41> errselrEL1;
+        Bitfield<40> erridrEL1; // RES0 for HFGWTR
+        Bitfield<39> iccIgrpEnEL1;
+        Bitfield<38> vbarEL1;
+        Bitfield<37> ttbr1EL1;
+        Bitfield<36> ttbr0EL1;
+        Bitfield<35> tpidrEL0;
+        Bitfield<34> tpidrroEL0;
+        Bitfield<33> tpidrEL1;
+        Bitfield<32> tcrEL1;
+        Bitfield<31> scxtnumEL0;
+        Bitfield<30> scxtnumEL1;
+        Bitfield<29> sctlrEL1;
+        Bitfield<28> revidrEL1; // RES0 for HFGWTR
+        Bitfield<27> parEL1;
+        Bitfield<26> mpidrEL1; // RES0 for HFGWTR
+        Bitfield<25> midrEL1; // RES0 for HFGWTR
+        Bitfield<24> mairEL1;
+        Bitfield<23> lorsaEL1;
+        Bitfield<22> lornEL1;
+        Bitfield<21> loridEL1; // RES0 for HFGWTR
+        Bitfield<20> loreaEL1;
+        Bitfield<19> lorcEL1;
+        Bitfield<18> isrEL1; // RES0 for HFGWTR
+        Bitfield<17> farEL1;
+        Bitfield<16> esrEL1;
+        Bitfield<15> dczidEL0; // RES0 for HFGWTR
+        Bitfield<14> ctrEL0; // RES0 for HFGWTR
+        Bitfield<13> csselrEL1;
+        Bitfield<12> cpacrEL1;
+        Bitfield<11> contextidrEL1;
+        Bitfield<10> clidrEL1; // RES0 for HFGWTR
+        Bitfield<9> ccsidrEL1; // RES0 for HFGWTR
+        Bitfield<8> apibKey;
+        Bitfield<7> apiaKey;
+        Bitfield<6> apgaKey;
+        Bitfield<5> apdbKey;
+        Bitfield<4> apdaKey;
+        Bitfield<3> amairEL1;
+        Bitfield<2> aidrEL1; // RES0 for HFGWTR
+        Bitfield<1> afsr1EL1;
+        Bitfield<0> afsr0EL1;
+    EndBitUnion(HFGTR)
+
 } // namespace ArmISA
 } // namespace gem5
 
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 2251d57c0b..f7b6cbf86b 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2017-2018, 2022 Arm Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018, 2022-2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -323,6 +323,7 @@ namespace ArmISA
         SMC_64                  = 0x17,
         TRAPPED_MSR_MRS_64      = 0x18,
         TRAPPED_SVE             = 0x19,
+        TRAPPED_ERET            = 0x1A,
         TRAPPED_SME             = 0x1D,
         PREFETCH_ABORT_TO_HYP   = 0x20,
         PREFETCH_ABORT_LOWER_EL = 0x20,  // AArch64 alias
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 05d1cab06c..9051eaa151 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2014, 2016-2020, 2022 Arm Limited
+ * Copyright (c) 2009-2014, 2016-2020, 2022-2023 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -1347,5 +1347,13 @@ syncVecElemsToRegs(ThreadContext *tc)
     }
 }
 
+bool
+fgtEnabled(ThreadContext *tc)
+{
+    return EL2Enabled(tc) && HaveExt(tc, ArmExtension::FEAT_FGT) &&
+        (!ArmSystem::haveEL(tc, EL3) ||
+            static_cast<SCR>(tc->readMiscReg(MISCREG_SCR_EL3)).fgten);
+}
+
 } // namespace ArmISA
 } // namespace gem5
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index b5a5dd72dd..d317651db5 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2016-2020, 2022 Arm Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -364,6 +364,8 @@ bool isUnpriviledgeAccess(ThreadContext *tc);
 void syncVecRegsToElems(ThreadContext *tc);
 void syncVecElemsToRegs(ThreadContext *tc);
 
+bool fgtEnabled(ThreadContext *tc);
+
 } // namespace ArmISA
 } // namespace gem5