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stdlib,arch-arm: Add ruby cache support to the ArmBoard

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This change adds ruby cache support to the ArmBoard. Previously
only classic caches were supported by the ArmBoard. The ArmBoard
was tested with CHI, MESI_Two_Level and MI_example caches from
the gem5's stdlib.

Change-Id: I480fe6ae13e3bd8438a425548ed113d443fcee40
Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64011
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Kaustav Goswami
2022-09-29 17:30:50 -07:00
committed by Bobby Bruce
parent 04ac9d9f4f
commit 75c1df0d06
4 changed files with 317 additions and 174 deletions
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20
configs/example/gem5_library/arm-ubuntu-boot-exit.py
View File

@@ -25,11 +25,10 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
"""
This script shows an example of booting an ARM based full system Ubuntu
disk image using the gem5's standard library. This simulation boots the disk
image using 2 TIMING CPU cores. The simulation ends when the startup is
completed successfully (i.e. when an `m5_exit instruction is reached on
successful boot).
This script further shows an example of booting an ARM based full system Ubuntu
disk image. This simulation boots the disk image using 2 TIMING CPU cores. The
simulation ends when the startup is completed successfully (i.e. when an
`m5_exit instruction is reached on successful boot).
Usage
-----
@@ -44,27 +43,26 @@ scons build/ARM/gem5.opt -j<NUM_CPUS>
from gem5.isas import ISA
from m5.objects import ArmDefaultRelease
from gem5.utils.requires import requires
from gem5.resources.workload import Workload
from gem5.simulate.simulator import Simulator
from m5.objects import VExpress_GEM5_Foundation
from gem5.coherence_protocol import CoherenceProtocol
from gem5.components.boards.arm_board import ArmBoard
from gem5.components.memory import DualChannelDDR4_2400
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.resources.workload import Workload
# This runs a check to ensure the gem5 binary is compiled for ARM.
# This runs a check to ensure the gem5 binary is compiled for ARM and the
# protocol is CHI.
requires(isa_required=ISA.ARM)
# With ARM, we use simple caches.
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
# Here we setup the parameters of the l1 and l2 caches.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
)