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arch-riscv: Fix Zcmp implement typos (#1727)

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Fix some typos from previous PR: https://github.com/gem5/gem5/pull/1432

Change-Id: I7126d0a20b3294c7f15d90f2d50842d20ddb5e40
This commit is contained in:
Yu-Cheng Chang
2024-10-31 00:47:30 +08:00
committed by GitHub
parent 24b672ab01
commit 757b272a25
1 changed files with 5 additions and 5 deletions
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10
src/arch/riscv/isa/formats/zcmp.isa
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@@ -248,8 +248,8 @@ def template SpAdjMicroExecute {{
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ' '
<< registerName(srcRegIdx(0)) << ' ' << adj;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
<< registerName(srcRegIdx(0)) << ", " << adj;
return ss.str();
}
}};
@@ -600,7 +600,7 @@ def template CmMvMicroExecute {{
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ' '
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
<< registerName(srcRegIdx(0));
return ss.str();
}
@@ -616,7 +616,7 @@ def format CmPush(*flags) {{
memacc_code = 'Mem_sw = CmPushReg_sw;'
ea_code = 'EA = rvSext(sp + offset);'
micro32_iop = InstObjParams('lw', f'{Name}32MicroInst', 'RiscvMicroInst',
micro32_iop = InstObjParams('sw', f'{Name}32MicroInst', 'RiscvMicroInst',
{'ea_code': ea_code, 'memacc_code': memacc_code},
flags)
@@ -632,7 +632,7 @@ def format CmPush(*flags) {{
memacc_code = 'Mem = CmPushReg;'
ea_code = 'EA = rvSext(sp + offset);'
micro64_iop = InstObjParams('ld', f'{Name}64MicroInst', 'RiscvMicroInst',
micro64_iop = InstObjParams('sd', f'{Name}64MicroInst', 'RiscvMicroInst',
{'ea_code': ea_code, 'memacc_code': memacc_code},
flags)