From 74ca89f8b7d9b340d1d4f83511b57a2dfa2a70df Mon Sep 17 00:00:00 2001 From: David Hashe Date: Mon, 20 Jul 2015 09:15:18 -0500 Subject: [PATCH] ruby: give access to cache tag/data latencies from SLICC This patch exposes the tag and data array latencies to the SLICC state machines so that it can be used to determine the correct enqueue latency for response messages. --- src/mem/protocol/RubySlicc_Types.sm | 2 ++ src/mem/ruby/structures/BankedArray.hh | 1 + src/mem/ruby/structures/CacheMemory.hh | 3 +++ 3 files changed, 6 insertions(+) diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index fb506781cc..88b9839bb4 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -149,6 +149,8 @@ structure (CacheMemory, external = "yes") { void deallocate(Address); AbstractCacheEntry lookup(Address); bool isTagPresent(Address); + Cycles getTagLatency(); + Cycles getDataLatency(); void setMRU(Address); void recordRequestType(CacheRequestType); bool checkResourceAvailable(CacheResourceType, Address); diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh index 5cc3eee32c..dbfee99940 100644 --- a/src/mem/ruby/structures/BankedArray.hh +++ b/src/mem/ruby/structures/BankedArray.hh @@ -70,6 +70,7 @@ class BankedArray // This is so we don't get aliasing on blocks being replaced bool tryAccess(int64 idx); + Cycles getLatency() const { return accessLatency; } }; #endif diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 4724da2b8a..647520566a 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -91,6 +91,9 @@ class CacheMemory : public SimObject const AbstractCacheEntry* lookup(const Address& address) const; Cycles getLatency() const { return m_latency; } + Cycles getTagLatency() const { return tagArray.getLatency(); } + Cycles getDataLatency() const { return dataArray.getLatency(); } + // Hook for checkpointing the contents of the cache void recordCacheContents(int cntrl, CacheRecorder* tr) const;