diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index a2f92683c4..5df00d3f39 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -1340,8 +1340,6 @@ Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard, *inst, ex_info.streamSeqNum); if (fault == NoFault) { - // output both old and new stats - cpu.stats.numDiscardedOps++; cpu.executeStats[thread_id]->numDiscardedOps++; } } diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc index 512a67bf36..818db8c360 100644 --- a/src/cpu/minor/stats.cc +++ b/src/cpu/minor/stats.cc @@ -49,9 +49,6 @@ MinorStats::MinorStats(BaseCPU *base_cpu) "Number of instructions committed"), ADD_STAT(numOps, statistics::units::Count::get(), "Number of ops (including micro ops) committed"), - ADD_STAT(numDiscardedOps, statistics::units::Count::get(), - "Number of ops (including micro ops) which were discarded before " - "commit"), ADD_STAT(quiesceCycles, statistics::units::Cycle::get(), "Total number of cycles that CPU has spent quiesced or waiting " "for an interrupt"), diff --git a/src/cpu/minor/stats.hh b/src/cpu/minor/stats.hh index 4ab8743c77..f7d5e71dfa 100644 --- a/src/cpu/minor/stats.hh +++ b/src/cpu/minor/stats.hh @@ -65,9 +65,6 @@ struct MinorStats : public statistics::Group /** Number of simulated insts and microops */ statistics::Scalar numOps; - /** Number of ops discarded before committing */ - statistics::Scalar numDiscardedOps; - /** Number of cycles in quiescent state */ statistics::Scalar quiesceCycles; diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc index 5a0a6b21e3..266e59e2e3 100644 --- a/src/cpu/o3/commit.cc +++ b/src/cpu/o3/commit.cc @@ -156,10 +156,6 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit) "The number of times a branch was mispredicted"), ADD_STAT(numCommittedDist, statistics::units::Count::get(), "Number of insts commited each cycle"), - ADD_STAT(instsCommitted, statistics::units::Count::get(), - "Number of instructions committed"), - ADD_STAT(opsCommitted, statistics::units::Count::get(), - "Number of ops (including micro ops) committed"), ADD_STAT(amos, statistics::units::Count::get(), "Number of atomic instructions committed"), ADD_STAT(membars, statistics::units::Count::get(), @@ -181,14 +177,6 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit) .init(0,commit->commitWidth,1) .flags(statistics::pdf); - instsCommitted - .init(cpu->numThreads) - .flags(total); - - opsCommitted - .init(cpu->numThreads) - .flags(total); - amos .init(cpu->numThreads) .flags(total); @@ -1351,13 +1339,9 @@ Commit::updateComInstStats(const DynInstPtr &inst) ThreadID tid = inst->threadNumber; if (!inst->isMicroop() || inst->isLastMicroop()) { - // update both old and new stats - stats.instsCommitted[tid]++; cpu->commitStats[tid]->numInsts++; cpu->baseStats.numInsts++; } - // update both old and new stats - stats.opsCommitted[tid]++; cpu->commitStats[tid]->numOps++; cpu->baseStats.numOps++; diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 6591360197..eccd023d45 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -479,10 +479,6 @@ class Commit /** Distribution of the number of committed instructions each cycle. */ statistics::Distribution numCommittedDist; - /** Total number of instructions committed. */ - statistics::Vector instsCommitted; - /** Total number of ops (including micro ops) committed. */ - statistics::Vector opsCommitted; /** Stat for the total number of committed atomics. */ statistics::Vector amos; /** Total number of committed memory barriers. */ diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 444692d47f..85cc3dbf71 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -328,47 +328,7 @@ CPU::CPUStats::CPUStats(CPU *cpu) "to idling"), ADD_STAT(quiesceCycles, statistics::units::Cycle::get(), "Total number of cycles that CPU has spent quiesced or waiting " - "for an interrupt"), - ADD_STAT(committedInsts, statistics::units::Count::get(), - "Number of Instructions Simulated"), - ADD_STAT(committedOps, statistics::units::Count::get(), - "Number of Ops (including micro ops) Simulated"), - ADD_STAT(cpi, statistics::units::Rate< - statistics::units::Cycle, statistics::units::Count>::get(), - "CPI: Cycles Per Instruction"), - ADD_STAT(totalCpi, statistics::units::Rate< - statistics::units::Cycle, statistics::units::Count>::get(), - "CPI: Total CPI of All Threads"), - ADD_STAT(ipc, statistics::units::Rate< - statistics::units::Count, statistics::units::Cycle>::get(), - "IPC: Instructions Per Cycle"), - ADD_STAT(totalIpc, statistics::units::Rate< - statistics::units::Count, statistics::units::Cycle>::get(), - "IPC: Total IPC of All Threads"), - ADD_STAT(intRegfileReads, statistics::units::Count::get(), - "Number of integer regfile reads"), - ADD_STAT(intRegfileWrites, statistics::units::Count::get(), - "Number of integer regfile writes"), - ADD_STAT(fpRegfileReads, statistics::units::Count::get(), - "Number of floating regfile reads"), - ADD_STAT(fpRegfileWrites, statistics::units::Count::get(), - "Number of floating regfile writes"), - ADD_STAT(vecRegfileReads, statistics::units::Count::get(), - "number of vector regfile reads"), - ADD_STAT(vecRegfileWrites, statistics::units::Count::get(), - "number of vector regfile writes"), - ADD_STAT(vecPredRegfileReads, statistics::units::Count::get(), - "number of predicate regfile reads"), - ADD_STAT(vecPredRegfileWrites, statistics::units::Count::get(), - "number of predicate regfile writes"), - ADD_STAT(ccRegfileReads, statistics::units::Count::get(), - "number of cc regfile reads"), - ADD_STAT(ccRegfileWrites, statistics::units::Count::get(), - "number of cc regfile writes"), - ADD_STAT(miscRegfileReads, statistics::units::Count::get(), - "number of misc regfile reads"), - ADD_STAT(miscRegfileWrites, statistics::units::Count::get(), - "number of misc regfile writes") + "for an interrupt") { // Register any of the O3CPU's stats here. timesIdled @@ -379,70 +339,6 @@ CPU::CPUStats::CPUStats(CPU *cpu) quiesceCycles .prereq(quiesceCycles); - - // Number of Instructions simulated - // -------------------------------- - // Should probably be in Base CPU but need templated - // MaxThreads so put in here instead - committedInsts - .init(cpu->numThreads) - .flags(statistics::total); - - committedOps - .init(cpu->numThreads) - .flags(statistics::total); - - cpi - .precision(6); - cpi = cpu->baseStats.numCycles / committedInsts; - - totalCpi - .precision(6); - totalCpi = cpu->baseStats.numCycles / sum(committedInsts); - - ipc - .precision(6); - ipc = committedInsts / cpu->baseStats.numCycles; - - totalIpc - .precision(6); - totalIpc = sum(committedInsts) / cpu->baseStats.numCycles; - - intRegfileReads - .prereq(intRegfileReads); - - intRegfileWrites - .prereq(intRegfileWrites); - - fpRegfileReads - .prereq(fpRegfileReads); - - fpRegfileWrites - .prereq(fpRegfileWrites); - - vecRegfileReads - .prereq(vecRegfileReads); - - vecRegfileWrites - .prereq(vecRegfileWrites); - - vecPredRegfileReads - .prereq(vecPredRegfileReads); - - vecPredRegfileWrites - .prereq(vecPredRegfileWrites); - - ccRegfileReads - .prereq(ccRegfileReads); - - ccRegfileWrites - .prereq(ccRegfileWrites); - - miscRegfileReads - .prereq(miscRegfileReads); - - miscRegfileWrites - .prereq(miscRegfileWrites); } void @@ -1019,9 +915,6 @@ CPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) const RegVal CPU::readMiscReg(int misc_reg, ThreadID tid) { - // output both old and new stats, keep - // return value the same - cpuStats.miscRegfileReads++; executeStats[tid]->numMiscRegReads++; return isa[tid]->readMiscReg(misc_reg); } @@ -1035,132 +928,10 @@ CPU::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) void CPU::setMiscReg(int misc_reg, RegVal val, ThreadID tid) { - // output both old and new stats - cpuStats.miscRegfileWrites++; executeStats[tid]->numMiscRegWrites++; isa[tid]->setMiscReg(misc_reg, val); } -RegVal -CPU::getReg(PhysRegIdPtr phys_reg) -{ - switch (phys_reg->classValue()) { - case IntRegClass: - cpuStats.intRegfileReads++; - break; - case FloatRegClass: - cpuStats.fpRegfileReads++; - break; - case CCRegClass: - cpuStats.ccRegfileReads++; - break; - case VecRegClass: - case VecElemClass: - cpuStats.vecRegfileReads++; - break; - case VecPredRegClass: - cpuStats.vecPredRegfileReads++; - break; - default: - break; - } - return regFile.getReg(phys_reg); -} - -void -CPU::getReg(PhysRegIdPtr phys_reg, void *val) -{ - switch (phys_reg->classValue()) { - case IntRegClass: - cpuStats.intRegfileReads++; - break; - case FloatRegClass: - cpuStats.fpRegfileReads++; - break; - case CCRegClass: - cpuStats.ccRegfileReads++; - break; - case VecRegClass: - case VecElemClass: - cpuStats.vecRegfileReads++; - break; - case VecPredRegClass: - cpuStats.vecPredRegfileReads++; - break; - default: - break; - } - regFile.getReg(phys_reg, val); -} - -void * -CPU::getWritableReg(PhysRegIdPtr phys_reg) -{ - switch (phys_reg->classValue()) { - case VecRegClass: - cpuStats.vecRegfileReads++; - break; - case VecPredRegClass: - cpuStats.vecPredRegfileReads++; - break; - default: - break; - } - return regFile.getWritableReg(phys_reg); -} - -void -CPU::setReg(PhysRegIdPtr phys_reg, RegVal val) -{ - switch (phys_reg->classValue()) { - case IntRegClass: - cpuStats.intRegfileWrites++; - break; - case FloatRegClass: - cpuStats.fpRegfileWrites++; - break; - case CCRegClass: - cpuStats.ccRegfileWrites++; - break; - case VecRegClass: - case VecElemClass: - cpuStats.vecRegfileWrites++; - break; - case VecPredRegClass: - cpuStats.vecPredRegfileWrites++; - break; - default: - break; - } - regFile.setReg(phys_reg, val); -} - -void -CPU::setReg(PhysRegIdPtr phys_reg, const void *val) -{ - switch (phys_reg->classValue()) { - case IntRegClass: - cpuStats.intRegfileWrites++; - break; - case FloatRegClass: - cpuStats.fpRegfileWrites++; - break; - case CCRegClass: - cpuStats.ccRegfileWrites++; - break; - case VecRegClass: - case VecElemClass: - cpuStats.vecRegfileWrites++; - break; - case VecPredRegClass: - cpuStats.vecPredRegfileWrites++; - break; - default: - break; - } - regFile.setReg(phys_reg, val); -} - RegVal CPU::getReg(PhysRegIdPtr phys_reg, ThreadID tid) { @@ -1353,19 +1124,15 @@ CPU::instDone(ThreadID tid, const DynInstPtr &inst) { // Keep an instruction count. if (!inst->isMicroop() || inst->isLastMicroop()) { - // update both old and new stats thread[tid]->numInst++; thread[tid]->threadStats.numInsts++; - cpuStats.committedInsts[tid]++; commitStats[tid]->numInstsNotNOP++; // Check for instruction-count-based events. thread[tid]->comInstEventQueue.serviceEvents(thread[tid]->numInst); } - // update both old and new stats thread[tid]->numOp++; thread[tid]->threadStats.numOps++; - cpuStats.committedOps[tid]++; commitStats[tid]->numOpsNotNOP++; probeInstCommit(inst->staticInst, inst->pcState().instAddr()); diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index d6317d6ea2..1d100ab330 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -310,18 +310,6 @@ class CPU : public BaseCPU */ void setMiscReg(int misc_reg, RegVal val, ThreadID tid); - RegVal getReg(PhysRegIdPtr phys_reg); - void getReg(PhysRegIdPtr phys_reg, void *val); - void *getWritableReg(PhysRegIdPtr phys_reg); - - void setReg(PhysRegIdPtr phys_reg, RegVal val); - void setReg(PhysRegIdPtr phys_reg, const void *val); - - /** These functions are duplicated so that one set - * doesn't use thread ID, while the other does. - * This allows us to still output both old and - * new versions of the stats. - */ RegVal getReg(PhysRegIdPtr phys_reg, ThreadID tid); void getReg(PhysRegIdPtr phys_reg, void *val, ThreadID tid); void *getWritableReg(PhysRegIdPtr phys_reg, ThreadID tid); @@ -593,38 +581,6 @@ class CPU : public BaseCPU /** Stat for total number of cycles the CPU spends descheduled due to a * quiesce operation or waiting for an interrupt. */ statistics::Scalar quiesceCycles; - /** Stat for the number of committed instructions per thread. */ - statistics::Vector committedInsts; - /** Stat for the number of committed ops (including micro ops) per - * thread. */ - statistics::Vector committedOps; - /** Stat for the CPI per thread. */ - statistics::Formula cpi; - /** Stat for the total CPI. */ - statistics::Formula totalCpi; - /** Stat for the IPC per thread. */ - statistics::Formula ipc; - /** Stat for the total IPC. */ - statistics::Formula totalIpc; - - //number of integer register file accesses - statistics::Scalar intRegfileReads; - statistics::Scalar intRegfileWrites; - //number of float register file accesses - statistics::Scalar fpRegfileReads; - statistics::Scalar fpRegfileWrites; - //number of vector register file accesses - mutable statistics::Scalar vecRegfileReads; - statistics::Scalar vecRegfileWrites; - //number of predicate register file accesses - mutable statistics::Scalar vecPredRegfileReads; - statistics::Scalar vecPredRegfileWrites; - //number of CC register file accesses - statistics::Scalar ccRegfileReads; - statistics::Scalar ccRegfileWrites; - //number of misc - statistics::Scalar miscRegfileReads; - statistics::Scalar miscRegfileWrites; } cpuStats; public: diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 4f762b4551..63bf5ac59d 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -1085,15 +1085,10 @@ class DynInst : public ExecContext, public RefCounted continue; if (bytes == sizeof(RegVal)) { - // call both old and new functions - setRegOperand(staticInst.get(), idx, - cpu->getReg(prev_phys_reg)); setRegOperand(staticInst.get(), idx, cpu->getReg(prev_phys_reg, threadNumber)); } else { uint8_t val[original_dest_reg.regClass().regBytes()]; - // call both old and new functions - cpu->getReg(prev_phys_reg, val); cpu->getReg(prev_phys_reg, val, threadNumber); setRegOperand(staticInst.get(), idx, val); } @@ -1121,9 +1116,7 @@ class DynInst : public ExecContext, public RefCounted const PhysRegIdPtr reg = renamedSrcIdx(idx); if (reg->is(InvalidRegClass)) return 0; - // call new function, only return old value - cpu->getReg(reg, threadNumber); - return cpu->getReg(reg); + return cpu->getReg(reg, threadNumber); } void @@ -1132,17 +1125,13 @@ class DynInst : public ExecContext, public RefCounted const PhysRegIdPtr reg = renamedSrcIdx(idx); if (reg->is(InvalidRegClass)) return; - // call both old and new function - cpu->getReg(reg, val); cpu->getReg(reg, val, threadNumber); } void * getWritableRegOperand(const StaticInst *si, int idx) override { - // call both old and new function return cpu->getWritableReg(renamedDestIdx(idx), threadNumber); - return cpu->getWritableReg(renamedDestIdx(idx)); } /** @todo: Make results into arrays so they can handle multiple dest @@ -1154,8 +1143,6 @@ class DynInst : public ExecContext, public RefCounted const PhysRegIdPtr reg = renamedDestIdx(idx); if (reg->is(InvalidRegClass)) return; - // call both old and new functions - cpu->setReg(reg, val); cpu->setReg(reg, val, threadNumber); setResult(reg->regClass(), val); } @@ -1166,8 +1153,6 @@ class DynInst : public ExecContext, public RefCounted const PhysRegIdPtr reg = renamedDestIdx(idx); if (reg->is(InvalidRegClass)) return; - // call both old and new functions - cpu->setReg(reg, val); cpu->setReg(reg, val, threadNumber); setResult(reg->regClass(), val); } diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc index 89d1b81197..8cd84cbf05 100644 --- a/src/cpu/o3/fetch.cc +++ b/src/cpu/o3/fetch.cc @@ -158,12 +158,6 @@ Fetch::regProbePoints() Fetch::FetchStatGroup::FetchStatGroup(CPU *cpu, Fetch *fetch) : statistics::Group(cpu, "fetch"), - ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(), - "Number of cycles fetch is stalled on an Icache miss"), - ADD_STAT(insts, statistics::units::Count::get(), - "Number of instructions fetch has processed"), - ADD_STAT(branches, statistics::units::Count::get(), - "Number of branches that fetch encountered"), ADD_STAT(predictedBranches, statistics::units::Count::get(), "Number of branches that fetch has predicted taken"), ADD_STAT(cycles, statistics::units::Cycle::get(), @@ -200,21 +194,8 @@ Fetch::FetchStatGroup::FetchStatGroup(CPU *cpu, Fetch *fetch) "Number of instructions fetched each cycle (Total)"), ADD_STAT(idleRate, statistics::units::Ratio::get(), "Ratio of cycles fetch was idle", - idleCycles / cpu->baseStats.numCycles), - ADD_STAT(branchRate, statistics::units::Ratio::get(), - "Number of branch fetches per cycle", - branches / cpu->baseStats.numCycles), - ADD_STAT(rate, statistics::units::Rate< - statistics::units::Count, statistics::units::Cycle>::get(), - "Number of inst fetches per cycle", - insts / cpu->baseStats.numCycles) + idleCycles / cpu->baseStats.numCycles) { - icacheStallCycles - .prereq(icacheStallCycles); - insts - .prereq(insts); - branches - .prereq(branches); predictedBranches .prereq(predictedBranches); cycles @@ -252,10 +233,6 @@ Fetch::FetchStatGroup::FetchStatGroup(CPU *cpu, Fetch *fetch) .flags(statistics::pdf); idleRate .prereq(idleRate); - branchRate - .flags(statistics::total); - rate - .flags(statistics::total); } void Fetch::setTimeBuffer(TimeBuffer *time_buffer) @@ -540,9 +517,7 @@ Fetch::lookupAndUpdateNextPC(const DynInstPtr &inst, PCStateBase &next_pc) inst->setPredTarg(next_pc); inst->setPredTaken(predict_taken); - // update both old and new stats cpu->fetchStats[tid]->numBranches++; - ++fetchStats.branches; if (predict_taken) { ++fetchStats.predictedBranches; @@ -1148,8 +1123,6 @@ Fetch::fetch(bool &status_change) fetchCacheLine(fetchAddr, tid, this_pc.instAddr()); if (fetchStatus[tid] == IcacheWaitResponse) { - // update both old and new stats - ++fetchStats.icacheStallCycles; cpu->fetchStats[tid]->icacheStallCycles++; } else if (fetchStatus[tid] == ItlbWait) @@ -1247,8 +1220,6 @@ Fetch::fetch(bool &status_change) staticInst = dec_ptr->decode(this_pc); // Increment stat of fetched instructions. - // Update both old and new stats - ++fetchStats.insts; cpu->fetchStats[tid]->numInsts++; if (staticInst->isMacroop()) { @@ -1579,9 +1550,7 @@ Fetch::profileStall(ThreadID tid) ++fetchStats.squashCycles; DPRINTF(Fetch, "[tid:%i] Fetch is squashing!\n", tid); } else if (fetchStatus[tid] == IcacheWaitResponse) { - // update both old and new stats cpu->fetchStats[tid]->icacheStallCycles++; - ++fetchStats.icacheStallCycles; DPRINTF(Fetch, "[tid:%i] Fetch is waiting cache response!\n", tid); } else if (fetchStatus[tid] == ItlbWait) { diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index cd311913f5..6add31444d 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -533,12 +533,6 @@ class Fetch FetchStatGroup(CPU *cpu, Fetch *fetch); // @todo: Consider making these // vectors and tracking on a per thread basis. - /** Stat for total number of cycles stalled due to an icache miss. */ - statistics::Scalar icacheStallCycles; - /** Stat for total number of fetched instructions. */ - statistics::Scalar insts; - /** Total number of fetched branches. */ - statistics::Scalar branches; /** Stat for total number of predicted branches. */ statistics::Scalar predictedBranches; /** Stat for total number of cycles spent fetching. */ @@ -581,10 +575,6 @@ class Fetch statistics::Distribution nisnDist; /** Rate of how often fetch was idle. */ statistics::Formula idleRate; - /** Number of branch fetches per cycle. */ - statistics::Formula branchRate; - /** Number of instruction fetched per cycle. */ - statistics::Formula rate; } fetchStats; }; diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc index 1b3598cea7..a8acb4c762 100644 --- a/src/cpu/o3/iew.cc +++ b/src/cpu/o3/iew.cc @@ -217,52 +217,14 @@ IEW::IEWStats::IEWStats(CPU *cpu) IEW::IEWStats::ExecutedInstStats::ExecutedInstStats(CPU *cpu) : statistics::Group(cpu), - ADD_STAT(numInsts, statistics::units::Count::get(), - "Number of executed instructions"), - ADD_STAT(numLoadInsts, statistics::units::Count::get(), - "Number of load instructions executed"), ADD_STAT(numSquashedInsts, statistics::units::Count::get(), "Number of squashed instructions skipped in execute"), ADD_STAT(numSwp, statistics::units::Count::get(), - "Number of swp insts executed"), - ADD_STAT(numNop, statistics::units::Count::get(), - "Number of nop insts executed"), - ADD_STAT(numRefs, statistics::units::Count::get(), - "Number of memory reference insts executed"), - ADD_STAT(numBranches, statistics::units::Count::get(), - "Number of branches executed"), - ADD_STAT(numStoreInsts, statistics::units::Count::get(), - "Number of stores executed"), - ADD_STAT(numRate, statistics::units::Rate< - statistics::units::Count, statistics::units::Cycle>::get(), - "Inst execution rate", numInsts / cpu->baseStats.numCycles) + "Number of swp insts executed") { - numLoadInsts - .init(cpu->numThreads) - .flags(statistics::total); - numSwp .init(cpu->numThreads) .flags(statistics::total); - - numNop - .init(cpu->numThreads) - .flags(statistics::total); - - numRefs - .init(cpu->numThreads) - .flags(statistics::total); - - numBranches - .init(cpu->numThreads) - .flags(statistics::total); - - numStoreInsts - .flags(statistics::total); - numStoreInsts = numRefs - numLoadInsts; - - numRate - .flags(statistics::total); } void @@ -1053,8 +1015,6 @@ IEW::dispatchInsts(ThreadID tid) instQueue.recordProducer(inst); - // update both old and new stats - iewStats.executedInstStats.numNop[tid]++; cpu->executeStats[tid]->numNop++; add_to_iq = false; @@ -1563,8 +1523,6 @@ IEW::updateExeInstStats(const DynInstPtr& inst) { ThreadID tid = inst->threadNumber; - // update both old and new stats - iewStats.executedInstStats.numInsts++; cpu->executeStats[tid]->numInsts++; #if TRACING_ON @@ -1577,8 +1535,6 @@ IEW::updateExeInstStats(const DynInstPtr& inst) // Control operations // if (inst->isControl()) { - // update both old and new stats - iewStats.executedInstStats.numBranches[tid]++; cpu->executeStats[tid]->numBranches++; } @@ -1586,13 +1542,9 @@ IEW::updateExeInstStats(const DynInstPtr& inst) // Memory operations // if (inst->isMemRef()) { - // update both old and new stats - iewStats.executedInstStats.numRefs[tid]++; cpu->executeStats[tid]->numMemRefs++; if (inst->isLoad()) { - // update both old and new stats - iewStats.executedInstStats.numLoadInsts[tid]++; cpu->executeStats[tid]->numLoadInsts++; } } diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index 80fed295df..4fe8227dcc 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -455,25 +455,11 @@ class IEW { ExecutedInstStats(CPU *cpu); - /** Stat for total number of executed instructions. */ - statistics::Scalar numInsts; - /** Stat for total number of executed load instructions. */ - statistics::Vector numLoadInsts; /** Stat for total number of squashed instructions skipped at * execute. */ statistics::Scalar numSquashedInsts; /** Number of executed software prefetches. */ statistics::Vector numSwp; - /** Number of executed nops. */ - statistics::Vector numNop; - /** Number of executed meomory references. */ - statistics::Vector numRefs; - /** Number of executed branches. */ - statistics::Vector numBranches; - /** Number of executed store instructions. */ - statistics::Formula numStoreInsts; - /** Number of instructions executed per cycle. */ - statistics::Formula numRate; } executedInstStats; /** Number of instructions sent to commit. */ diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index eeb927ffed..ca86b0b412 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -421,8 +421,6 @@ BaseSimpleCPU::postExecute() Addr instAddr = threadContexts[curThread]->pcState().instAddr(); if (curStaticInst->isMemRef()) { - // update both old and new stats - t_info.execContextStats.numMemRefs++; executeStats[t_info.thread->threadId()]->numMemRefs++; } @@ -439,21 +437,18 @@ BaseSimpleCPU::postExecute() if (curStaticInst->isInteger()){ executeStats[t_info.thread->threadId()]->numIntAluAccesses++; commitStats[t_info.thread->threadId()]->numIntInsts++; - t_info.execContextStats.numIntAluAccesses++; } //float alu accesses if (curStaticInst->isFloating()){ executeStats[t_info.thread->threadId()]->numFpAluAccesses++; commitStats[t_info.thread->threadId()]->numFpInsts++; - t_info.execContextStats.numFpAluAccesses++; } //vector alu accesses if (curStaticInst->isVector()){ executeStats[t_info.thread->threadId()]->numVecAluAccesses++; commitStats[t_info.thread->threadId()]->numVecInsts++; - t_info.execContextStats.numVecAluAccesses++; } //Matrix alu accesses diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 78952cbe75..9639f43058 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -90,44 +90,12 @@ class SimpleExecContext : public ExecContext "Number of instructions committed"), ADD_STAT(numOps, statistics::units::Count::get(), "Number of ops (including micro ops) committed"), - ADD_STAT(numIntAluAccesses, statistics::units::Count::get(), - "Number of integer alu accesses"), - ADD_STAT(numFpAluAccesses, statistics::units::Count::get(), - "Number of float alu accesses"), - ADD_STAT(numVecAluAccesses, statistics::units::Count::get(), - "Number of vector alu accesses"), ADD_STAT(numMatAluAccesses, statistics::units::Count::get(), "Number of matrix alu accesses"), ADD_STAT(numCallsReturns, statistics::units::Count::get(), "Number of times a function call or return occured"), ADD_STAT(numMatInsts, statistics::units::Count::get(), "Number of matrix instructions"), - ADD_STAT(numIntRegReads, statistics::units::Count::get(), - "Number of times the integer registers were read"), - ADD_STAT(numIntRegWrites, statistics::units::Count::get(), - "Number of times the integer registers were written"), - ADD_STAT(numFpRegReads, statistics::units::Count::get(), - "Number of times the floating registers were read"), - ADD_STAT(numFpRegWrites, statistics::units::Count::get(), - "Number of times the floating registers were written"), - ADD_STAT(numVecRegReads, statistics::units::Count::get(), - "Number of times the vector registers were read"), - ADD_STAT(numVecRegWrites, statistics::units::Count::get(), - "Number of times the vector registers were written"), - ADD_STAT(numVecPredRegReads, statistics::units::Count::get(), - "Number of times the predicate registers were read"), - ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(), - "Number of times the predicate registers were written"), - ADD_STAT(numCCRegReads, statistics::units::Count::get(), - "Number of times the CC registers were read"), - ADD_STAT(numCCRegWrites, statistics::units::Count::get(), - "Number of times the CC registers were written"), - ADD_STAT(numMiscRegReads, statistics::units::Count::get(), - "Number of times the Misc registers were read"), - ADD_STAT(numMiscRegWrites, statistics::units::Count::get(), - "Number of times the Misc registers were written"), - ADD_STAT(numMemRefs, statistics::units::Count::get(), - "Number of memory refs"), ADD_STAT(numIdleCycles, statistics::units::Cycle::get(), "Number of idle cycles"), ADD_STAT(numBusyCycles, statistics::units::Cycle::get(), @@ -136,10 +104,6 @@ class SimpleExecContext : public ExecContext "Percentage of non-idle cycles"), ADD_STAT(idleFraction, statistics::units::Ratio::get(), "Percentage of idle cycles"), - ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(), - "ICache total stall cycles"), - ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(), - "DCache total stall cycles"), ADD_STAT(numPredictedBranches, statistics::units::Count::get(), "Number of branches predicted as taken"), ADD_STAT(numBranchMispred, statistics::units::Count::get(), @@ -164,18 +128,6 @@ class SimpleExecContext : public ExecContext &numMatRegWrites } { - numCCRegReads - .flags(statistics::nozero); - - numCCRegWrites - .flags(statistics::nozero); - - icacheStallCycles - .prereq(icacheStallCycles); - - dcacheStallCycles - .prereq(dcacheStallCycles); - idleFraction = statistics::constant(1.0) - notIdleFraction; numIdleCycles = idleFraction * cpu->baseStats.numCycles; numBusyCycles = notIdleFraction * cpu->baseStats.numCycles; @@ -191,15 +143,6 @@ class SimpleExecContext : public ExecContext statistics::Scalar numInsts; statistics::Scalar numOps; - // Number of integer alu accesses - statistics::Scalar numIntAluAccesses; - - // Number of float alu accesses - statistics::Scalar numFpAluAccesses; - - // Number of vector alu accesses - statistics::Scalar numVecAluAccesses; - // Number of matrix alu accesses statistics::Scalar numMatAluAccesses; @@ -209,37 +152,10 @@ class SimpleExecContext : public ExecContext // Number of matrix instructions statistics::Scalar numMatInsts; - // Number of integer register file accesses - statistics::Scalar numIntRegReads; - statistics::Scalar numIntRegWrites; - - // Number of float register file accesses - statistics::Scalar numFpRegReads; - statistics::Scalar numFpRegWrites; - - // Number of vector register file accesses - mutable statistics::Scalar numVecRegReads; - statistics::Scalar numVecRegWrites; - - // Number of predicate register file accesses - mutable statistics::Scalar numVecPredRegReads; - statistics::Scalar numVecPredRegWrites; - // Number of matrix register file accesses mutable statistics::Scalar numMatRegReads; statistics::Scalar numMatRegWrites; - // Number of condition code register file accesses - statistics::Scalar numCCRegReads; - statistics::Scalar numCCRegWrites; - - // Number of misc register file accesses - statistics::Scalar numMiscRegReads; - statistics::Scalar numMiscRegWrites; - - // Number of simulated memory references - statistics::Scalar numMemRefs; - // Number of idle cycles statistics::Formula numIdleCycles; @@ -250,12 +166,6 @@ class SimpleExecContext : public ExecContext statistics::Average notIdleFraction; statistics::Formula idleFraction; - // Number of cycles stalled for I-cache responses - statistics::Scalar icacheStallCycles; - - // Number of cycles stalled for D-cache responses - statistics::Scalar dcacheStallCycles; - /// @{ /// Number of branches predicted as taken statistics::Scalar numPredictedBranches; @@ -323,8 +233,6 @@ class SimpleExecContext : public ExecContext RegVal readMiscRegOperand(const StaticInst *si, int idx) override { - // update both old and new stats - execContextStats.numMiscRegReads++; cpu->executeStats[thread->threadId()]->numMiscRegReads++; const RegId& reg = si->srcRegIdx(idx); assert(reg.is(MiscRegClass)); @@ -334,8 +242,6 @@ class SimpleExecContext : public ExecContext void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override { - // update both old and new stats - execContextStats.numMiscRegWrites++; cpu->executeStats[thread->threadId()]->numMiscRegWrites++; const RegId& reg = si->destRegIdx(idx); assert(reg.is(MiscRegClass)); @@ -349,8 +255,6 @@ class SimpleExecContext : public ExecContext RegVal readMiscReg(int misc_reg) override { - // update both old and new stats - execContextStats.numMiscRegReads++; cpu->executeStats[thread->threadId()]->numMiscRegReads++; return thread->readMiscReg(misc_reg); } @@ -362,8 +266,6 @@ class SimpleExecContext : public ExecContext void setMiscReg(int misc_reg, RegVal val) override { - // update both old and new stats - execContextStats.numMiscRegWrites++; cpu->executeStats[thread->threadId()]->numMiscRegWrites++; thread->setMiscReg(misc_reg, val); }