From 7395b94c40a1b291e29f96b375448f799b969791 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 18 Sep 2023 09:51:47 +0100
Subject: [PATCH] configs: Add a SimpleSeSystem class to devices.py

Change-Id: I9d120fbaf0c61c5a053163ec1e5f4f93c583df52
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
---
 configs/example/arm/devices.py | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 03d0a84799..7ceb3cd3bf 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -382,6 +382,30 @@ class ClusterSystem:
             cluster.connectMemSide(cluster_mem_bus)
 
 
+class SimpleSeSystem(System, ClusterSystem):
+    """
+    Example system class for syscall emulation mode
+    """
+
+    # Use a fixed cache line size of 64 bytes
+    cache_line_size = 64
+
+    def __init__(self, **kwargs):
+        System.__init__(self, **kwargs)
+        ClusterSystem.__init__(self, **kwargs)
+        # Create a voltage and clock domain for system components
+        self.voltage_domain = VoltageDomain(voltage="3.3V")
+        self.clk_domain = SrcClockDomain(
+            clock="1GHz", voltage_domain=self.voltage_domain
+        )
+
+        # Create the off-chip memory bus.
+        self.membus = SystemXBar()
+
+    def connect(self):
+        self.system_port = self.membus.cpu_side_ports
+
+
 class BaseSimpleSystem(ArmSystem, ClusterSystem):
     cache_line_size = 64