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arch,cpu,mem,sim: Reimplement the SE translating proxy using the FS one.

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The only functional difference between them was that the SE one might
have optionally fixed up missing translations for demand paging.

This lets us get rid of some code recreating the proxy ports in
setProcessPtr since the SE translating port no longer keeps a copy of
the process object pointer.

Change-Id: Id97df1874f1de138ffd4f2dbb5846dda79d9e4ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26550
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2020-03-09 16:50:32 -07:00
parent 8e0e7da5ab
commit 7342bccd8d
15 changed files with 122 additions and 216 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
src/mem/fs_translating_port_proxy.cc
View File

@@ -45,7 +45,6 @@
#include "mem/fs_translating_port_proxy.hh"
#include "arch/generic/tlb.hh"
#include "base/chunk_generator.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
@@ -58,21 +57,35 @@ FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc) :
{}
bool
FSTranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
FSTranslatingPortProxy::tryTLBsOnce(RequestPtr req, BaseTLB::Mode mode) const
{
BaseTLB *dtb = _tc->getDTBPtr();
BaseTLB *itb = _tc->getDTBPtr();
return dtb->translateFunctional(req, _tc, mode) == NoFault ||
itb->translateFunctional(req, _tc, BaseTLB::Read) == NoFault;
}
bool
FSTranslatingPortProxy::tryTLBs(RequestPtr req, BaseTLB::Mode mode) const
{
// If at first this doesn't succeed, try to fixup and translate again. If
// it still fails, report failure.
return tryTLBsOnce(req, mode) ||
(fixupAddr(req->getVaddr(), mode) && tryTLBsOnce(req, mode));
}
bool
FSTranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
{
for (ChunkGenerator gen(addr, size, pageBytes); !gen.done();
gen.next())
{
auto req = std::make_shared<Request>(
gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
_tc->contextId());
if (dtb->translateFunctional(req, _tc, BaseTLB::Read) != NoFault &&
itb->translateFunctional(req, _tc, BaseTLB::Read) != NoFault) {
if (!tryTLBs(req, BaseTLB::Read))
return false;
}
PortProxy::readBlobPhys(
req->getPaddr(), req->getFlags(), p, gen.size());
@@ -86,19 +99,15 @@ bool
FSTranslatingPortProxy::tryWriteBlob(
Addr addr, const void *p, int size) const
{
BaseTLB *dtb = _tc->getDTBPtr();
BaseTLB *itb = _tc->getDTBPtr();
for (ChunkGenerator gen(addr, size, pageBytes); !gen.done();
gen.next())
{
auto req = std::make_shared<Request>(
gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
_tc->contextId());
if (dtb->translateFunctional(req, _tc, BaseTLB::Write) != NoFault &&
itb->translateFunctional(req, _tc, BaseTLB::Write) != NoFault) {
if (!tryTLBs(req, BaseTLB::Write))
return false;
}
PortProxy::writeBlobPhys(
req->getPaddr(), req->getFlags(), p, gen.size());
@@ -110,19 +119,15 @@ FSTranslatingPortProxy::tryWriteBlob(
bool
FSTranslatingPortProxy::tryMemsetBlob(Addr address, uint8_t v, int size) const
{
BaseTLB *dtb = _tc->getDTBPtr();
BaseTLB *itb = _tc->getDTBPtr();
for (ChunkGenerator gen(address, size, pageBytes); !gen.done();
gen.next())
{
auto req = std::make_shared<Request>(
gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
_tc->contextId());
if (dtb->translateFunctional(req, _tc, BaseTLB::Write) != NoFault &&
itb->translateFunctional(req, _tc, BaseTLB::Write) != NoFault) {
if (!tryTLBs(req, BaseTLB::Write))
return false;
}
PortProxy::memsetBlobPhys(
req->getPaddr(), req->getFlags(), v, gen.size());

20
src/mem/fs_translating_port_proxy.hh
View File

@@ -56,23 +56,33 @@
#ifndef __MEM_FS_TRANSLATING_PORT_PROXY_HH__
#define __MEM_FS_TRANSLATING_PORT_PROXY_HH__
#include "arch/generic/tlb.hh"
#include "mem/port_proxy.hh"
class ThreadContext;
/**
* A TranslatingPortProxy in FS mode translates a virtual address to a
* physical address and then calls the read/write functions of the
* port. If a thread context is provided the address can alway be
* translated, If not it can only be translated if it is a simple
* address masking operation (such as alpha super page accesses).
* This proxy attempts to translate virtual addresses using the TLBs. If it
* fails, subclasses can override the fixupAddr virtual method to try to
* recover, and then attempt the translation again. If it still fails then the
* access as a whole fails.
*/
class FSTranslatingPortProxy : public PortProxy
{
private:
bool tryTLBsOnce(RequestPtr req, BaseTLB::Mode) const;
bool tryTLBs(RequestPtr req, BaseTLB::Mode) const;
protected:
ThreadContext* _tc;
const Addr pageBytes;
virtual bool
fixupAddr(Addr addr, BaseTLB::Mode mode) const
{
return false;
}
public:
FSTranslatingPortProxy(ThreadContext* tc);

98
src/mem/se_translating_port_proxy.cc
View File

@@ -40,98 +40,28 @@
#include "mem/se_translating_port_proxy.hh"
#include <string>
#include "arch/isa_traits.hh"
#include "base/chunk_generator.hh"
#include "config/the_isa.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/system.hh"
using namespace TheISA;
SETranslatingPortProxy::SETranslatingPortProxy(
SendFunctionalFunc func, Process *p, AllocType alloc)
: PortProxy(func, p->system->cacheLineSize()), pTable(p->pTable),
process(p), allocating(alloc)
{ }
SETranslatingPortProxy::SETranslatingPortProxy(MasterPort &port,
Process *p, AllocType alloc)
: PortProxy(port, p->system->cacheLineSize()), pTable(p->pTable),
process(p), allocating(alloc)
{ }
ThreadContext *tc, AllocType alloc)
: FSTranslatingPortProxy(tc), allocating(alloc)
{}
bool
SETranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
SETranslatingPortProxy::fixupAddr(Addr addr, BaseTLB::Mode mode) const
{
int prevSize = 0;
auto *bytes = static_cast<uint8_t *>(p);
auto *process = _tc->getProcessPtr();
for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(),paddr))
return false;
PortProxy::readBlobPhys(paddr, 0, bytes + prevSize, gen.size());
prevSize += gen.size();
}
return true;
}
bool
SETranslatingPortProxy::tryWriteBlob(Addr addr, const void *p, int size) const
{
int prevSize = 0;
auto *bytes = static_cast<const uint8_t *>(p);
for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
if (allocating == Always) {
process->allocateMem(roundDown(gen.addr(), PageBytes),
PageBytes);
} else if (allocating == NextPage) {
// check if we've accessed the next page on the stack
if (!process->fixupStackFault(gen.addr()))
panic("Page table fault when accessing virtual address %#x "
"during functional write\n", gen.addr());
} else {
return false;
}
pTable->translate(gen.addr(), paddr);
if (mode == BaseTLB::Write) {
if (allocating == Always) {
process->allocateMem(roundDown(addr, pageBytes), pageBytes);
return true;
} else if (allocating == NextPage && process->fixupStackFault(addr)) {
// We've accessed the next page on the stack.
return true;
}
PortProxy::writeBlobPhys(paddr, 0, bytes + prevSize, gen.size());
prevSize += gen.size();
}
return true;
}
bool
SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) const
{
for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
if (allocating == Always) {
process->allocateMem(roundDown(gen.addr(), PageBytes),
PageBytes);
pTable->translate(gen.addr(), paddr);
} else {
return false;
}
}
PortProxy::memsetBlobPhys(paddr, 0, val, gen.size());
}
return true;
panic("Page table fault when accessing virtual address %#x "
"during functional write.", addr);
}

37
src/mem/se_translating_port_proxy.hh
View File

@@ -41,26 +41,9 @@
#ifndef __MEM_SE_TRANSLATING_PORT_PROXY_HH__
#define __MEM_SE_TRANSLATING_PORT_PROXY_HH__
#include "mem/port_proxy.hh"
#include "mem/fs_translating_port_proxy.hh"
class EmulationPageTable;
class Process;
/**
* @file
* TranslatingPortProxy Object Declaration for SE.
*
* Port proxies are used when non structural entities need access to
* the memory system. Proxy objects replace the previous
* FunctionalPort, TranslatingPort and VirtualPort objects, which
* provided the same functionality as the proxies, but were instances
* of ports not corresponding to real structural ports of the
* simulated system. Via the port proxies all the accesses go through
* an actual port and thus are transparent to a potentially
* distributed memory and automatically adhere to the memory map of
* the system.
*/
class SETranslatingPortProxy : public PortProxy
class SETranslatingPortProxy : public FSTranslatingPortProxy
{
public:
@@ -71,21 +54,13 @@ class SETranslatingPortProxy : public PortProxy
};
private:
EmulationPageTable *pTable;
Process *process;
AllocType allocating;
public:
SETranslatingPortProxy(SendFunctionalFunc func,
Process* p, AllocType alloc);
SETranslatingPortProxy(MasterPort &port, Process* p, AllocType alloc);
~SETranslatingPortProxy() {}
protected:
bool fixupAddr(Addr addr, BaseTLB::Mode mode) const override;
void setPageTable(EmulationPageTable *p) { pTable = p; }
void setProcess(Process *p) { process = p; }
bool tryReadBlob(Addr addr, void *p, int size) const override;
bool tryWriteBlob(Addr addr, const void *p, int size) const override;
bool tryMemsetBlob(Addr addr, uint8_t val, int size) const override;
public:
SETranslatingPortProxy(ThreadContext *tc, AllocType alloc);
};
#endif // __MEM_SE_TRANSLATING_PORT_PROXY_HH__