arch,cpu,mem,sim: Reimplement the SE translating proxy using the FS one.

The only functional difference between them was that the SE one might
have optionally fixed up missing translations for demand paging.

This lets us get rid of some code recreating the proxy ports in
setProcessPtr since the SE translating port no longer keeps a copy of
the process object pointer.

Change-Id: Id97df1874f1de138ffd4f2dbb5846dda79d9e4ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26550
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2020-03-09 16:50:32 -07:00
parent 8e0e7da5ab
commit 7342bccd8d
15 changed files with 122 additions and 216 deletions

View File

@@ -93,8 +93,8 @@ PowerProcess::argsInit(int intSize, int pageSize)
uint64_t align = 16;
// load object file into target memory
image.write(initVirtMem);
interpImage.write(initVirtMem);
image.write(*initVirtMem);
interpImage.write(*initVirtMem);
//Setup the auxilliary vectors. These will already have endian conversion.
//Auxilliary vectors are loaded only for elf formatted executables.
@@ -227,36 +227,36 @@ PowerProcess::argsInit(int intSize, int pageSize)
//Write out the sentry void *
uint32_t sentry_NULL = 0;
initVirtMem.writeBlob(sentry_base, &sentry_NULL, sentry_size);
initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);
//Fix up the aux vectors which point to other data
for (int i = auxv.size() - 1; i >= 0; i--) {
if (auxv[i].type == M5_AT_PLATFORM) {
auxv[i].val = platform_base;
initVirtMem.writeString(platform_base, platform.c_str());
initVirtMem->writeString(platform_base, platform.c_str());
} else if (auxv[i].type == M5_AT_EXECFN) {
auxv[i].val = aux_data_base;
initVirtMem.writeString(aux_data_base, filename.c_str());
initVirtMem->writeString(aux_data_base, filename.c_str());
}
}
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxilliary vector
const AuxVector<uint64_t> zero(0, 0);
initVirtMem.write(auxv_array_end, zero);
initVirtMem->write(auxv_array_end, zero);
auxv_array_end += sizeof(zero);
copyStringArray(envp, envp_array_base, env_data_base,
BigEndianByteOrder, initVirtMem);
BigEndianByteOrder, *initVirtMem);
copyStringArray(argv, argv_array_base, arg_data_base,
BigEndianByteOrder, initVirtMem);
BigEndianByteOrder, *initVirtMem);
initVirtMem.writeBlob(argc_base, &guestArgc, intSize);
initVirtMem->writeBlob(argc_base, &guestArgc, intSize);
ThreadContext *tc = system->getThreadContext(contextIds[0]);