From 7315bf685a9a2bb0752701ad3bba588e9259c9c1 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabe.black@gmail.com>
Date: Sat, 27 Feb 2021 02:19:17 -0800
Subject: [PATCH] cpu: Style fixes in the base and O3 dynamic inst classes.

Change-Id: Idfd8e71856931fa101e00c58a2aa4018d6666076
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42093
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/cpu/base_dyn_inst.hh | 15 +++++++++++----
 src/cpu/o3/dyn_inst.hh   | 32 ++++++++++++++++----------------
 2 files changed, 27 insertions(+), 20 deletions(-)

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 68a6bb3278..a5a842a50e 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -729,8 +729,11 @@ class BaseDynInst : public ExecContext, public RefCounted
     OpClass opClass() const { return staticInst->opClass(); }
 
     /** Returns the branch target address. */
-    TheISA::PCState branchTarget() const
-    { return staticInst->branchTarget(pc); }
+    TheISA::PCState
+    branchTarget() const
+    {
+        return staticInst->branchTarget(pc);
+    }
 
     /** Returns the number of source registers. */
     size_t numSrcRegs() const { return regs.numSrcs(); }
@@ -1016,11 +1019,15 @@ class BaseDynInst : public ExecContext, public RefCounted
 
     /** Return whether dest registers' pinning status updated after squash */
     bool
-    isPinnedRegsSquashDone() const { return status[PinnedRegsSquashDone]; }
+    isPinnedRegsSquashDone() const
+    {
+        return status[PinnedRegsSquashDone];
+    }
 
     /** Sets dest registers' status updated after squash */
     void
-    setPinnedRegsSquashDone() {
+    setPinnedRegsSquashDone()
+    {
         assert(!status[PinnedRegsSquashDone]);
         status.set(PinnedRegsSquashDone);
     }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index f084368676..7a54c7fd9b 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -184,37 +184,37 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         this->thread->noSquashFromTC = no_squash_from_TC;
     }
 
-    void forwardOldRegs()
+    void
+    forwardOldRegs()
     {
 
         for (int idx = 0; idx < this->numDestRegs(); idx++) {
             PhysRegIdPtr prev_phys_reg = this->regs.prevDestIdx(idx);
-            const RegId& original_dest_reg =
-                this->staticInst->destRegIdx(idx);
+            const RegId& original_dest_reg = this->staticInst->destRegIdx(idx);
             switch (original_dest_reg.classValue()) {
               case IntRegClass:
                 this->setIntRegOperand(this->staticInst.get(), idx,
-                               this->cpu->readIntReg(prev_phys_reg));
+                        this->cpu->readIntReg(prev_phys_reg));
                 break;
               case FloatRegClass:
                 this->setFloatRegOperandBits(this->staticInst.get(), idx,
-                               this->cpu->readFloatReg(prev_phys_reg));
+                        this->cpu->readFloatReg(prev_phys_reg));
                 break;
               case VecRegClass:
                 this->setVecRegOperand(this->staticInst.get(), idx,
-                               this->cpu->readVecReg(prev_phys_reg));
+                        this->cpu->readVecReg(prev_phys_reg));
                 break;
               case VecElemClass:
                 this->setVecElemOperand(this->staticInst.get(), idx,
-                               this->cpu->readVecElem(prev_phys_reg));
+                        this->cpu->readVecElem(prev_phys_reg));
                 break;
               case VecPredRegClass:
                 this->setVecPredRegOperand(this->staticInst.get(), idx,
-                               this->cpu->readVecPredReg(prev_phys_reg));
+                        this->cpu->readVecPredReg(prev_phys_reg));
                 break;
               case CCRegClass:
                 this->setCCRegOperand(this->staticInst.get(), idx,
-                               this->cpu->readCCReg(prev_phys_reg));
+                        this->cpu->readCCReg(prev_phys_reg));
                 break;
               case MiscRegClass:
                 // no need to forward misc reg values
@@ -309,25 +309,25 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     {
         return cpu->template setVecLane(this->regs.renamedDestIdx(idx), val);
     }
-    virtual void
+    void
     setVecLaneOperand(const StaticInst *si, int idx,
             const LaneData<LaneSize::Byte>& val) override
     {
         return setVecLaneOperandT(si, idx, val);
     }
-    virtual void
+    void
     setVecLaneOperand(const StaticInst *si, int idx,
             const LaneData<LaneSize::TwoByte>& val) override
     {
         return setVecLaneOperandT(si, idx, val);
     }
-    virtual void
+    void
     setVecLaneOperand(const StaticInst *si, int idx,
             const LaneData<LaneSize::FourByte>& val) override
     {
         return setVecLaneOperandT(si, idx, val);
     }
-    virtual void
+    void
     setVecLaneOperand(const StaticInst *si, int idx,
             const LaneData<LaneSize::EightByte>& val) override
     {
@@ -402,12 +402,12 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
     }
 
-    void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
+    void
+    setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         this->cpu->setCCReg(this->regs.renamedDestIdx(idx), val);
         BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
     }
 };
 
-#endif // __CPU_O3_ALPHA_DYN_INST_HH__
-
+#endif // __CPU_O3_DYN_INST_HH__