gcc: Clean-up of non-C++0x compliant code, first steps

This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).

src/cpu/base_dyn_inst.hh

@@ -96,7 +96,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
     };
 
     /** The StaticInst used by this BaseDynInst. */

src/cpu/exetrace.cc

@@ -171,4 +171,4 @@ Trace::ExeTracer *
 ExeTracerParams::create()
 {
     return new Trace::ExeTracer(this);
-};
+}

src/cpu/inorder/inorder_dyn_inst.hh

@@ -103,7 +103,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
     };
 
   public:

src/cpu/inorder/pipeline_traits.hh

@@ -77,7 +77,7 @@ namespace ThePipeline {
     //////////////////////////
     typedef ResourceSked ResSchedule;
     typedef ResourceSked* RSkedPtr;
-};
+}
 
 
 

src/cpu/inorder/resource.hh

@@ -263,7 +263,7 @@ class ResourceEvent : public Event
     /// (for InOrderCPU model).
     /// check src/sim/eventq.hh for more event priorities.
     enum InOrderPriority {
-        Resource_Event_Pri = 45,
+        Resource_Event_Pri = 45
     };
 
     /** The Resource Slot that this event is servicing */

src/cpu/inteltrace.cc

@@ -67,4 +67,4 @@ Trace::IntelTrace *
 IntelTraceParams::create()
 {
     return new Trace::IntelTrace(this);
-};
+}

src/cpu/o3/dyn_inst.hh

@@ -81,7 +81,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
     };
 
   public:

src/cpu/o3/thread_context.hh

@@ -50,7 +50,7 @@
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
-};
+}
 
 /**
  * Derived ThreadContext class for use with the O3CPU.  It

src/cpu/simple_thread.hh

@@ -73,8 +73,8 @@ class ProfileNode;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 /**
  * The SimpleThread object provides a combination of the ThreadState

src/cpu/static_inst.hh

@@ -87,7 +87,7 @@ class StaticInst : public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
     };
 
     /// Set of boolean static instruction properties.

src/cpu/thread_context.hh

@@ -70,8 +70,8 @@ class System;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 /**
  * ThreadContext is the external interface to all thread state for

src/cpu/thread_state.hh

@@ -45,8 +45,8 @@ class ProfileNode;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 class Checkpoint;