gcc: Clean-up of non-C++0x compliant code, first steps

This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).

src/arch/alpha/isa/main.isa

@@ -222,7 +222,7 @@ output header {{
         /// this class and derived classes.  Maybe these should really
         /// live here and not in the AlphaISA namespace.
         enum DependenceTags {
-            FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
+            FP_Base_DepTag = AlphaISA::FP_Base_DepTag
         };
 
         /// Constructor.

src/arch/alpha/isa_traits.hh

@@ -119,7 +119,7 @@ enum {
     MachineBytes = 8,
     WordBytes = 4,
     HalfwordBytes = 2,
-    ByteBytes = 1,
+    ByteBytes = 1
 };
 
 // return a no-op instruction... used for instruction fetch faults

src/arch/alpha/types.hh

@@ -48,7 +48,7 @@ enum annotes
 {
     ANNOTE_NONE = 0,
     // An impossible number for instruction annotations
-    ITOUCH_ANNOTE = 0xffffffff,
+    ITOUCH_ANNOTE = 0xffffffff
 };
 
 } // namespace AlphaISA

src/arch/arm/intregs.hh

@@ -239,7 +239,7 @@ enum IntRegIndex
     INTREG_R6_FIQ = INTREG_R6,
     INTREG_R7_FIQ = INTREG_R7,
     INTREG_PC_FIQ = INTREG_PC,
-    INTREG_R15_FIQ = INTREG_R15,
+    INTREG_R15_FIQ = INTREG_R15
 };
 
 typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];

src/arch/arm/isa/templates/neon.isa

@@ -234,12 +234,16 @@ def template NeonEqualRegExecute {{
 }};
 
 output header {{
-    uint16_t nextBiggerType(uint8_t);
-    uint32_t nextBiggerType(uint16_t);
-    uint64_t nextBiggerType(uint32_t);
-    int16_t nextBiggerType(int8_t);
-    int32_t nextBiggerType(int16_t);
-    int64_t nextBiggerType(int32_t);
+        template <typename T>
+            struct bigger_type_t;
+
+        template<> struct bigger_type_t<uint8_t> { typedef uint16_t type; };
+        template<> struct bigger_type_t<uint16_t> { typedef uint32_t type; };
+        template<> struct bigger_type_t<uint32_t> { typedef uint64_t type; };
+
+        template<> struct bigger_type_t<int8_t> { typedef int16_t type; };
+        template<> struct bigger_type_t<int16_t> { typedef int32_t type; };
+        template<> struct bigger_type_t<int32_t> { typedef int64_t type; };
 }};
 
 def template NeonUnequalRegExecute {{
@@ -247,7 +251,7 @@ def template NeonUnequalRegExecute {{
     Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
             Trace::InstRecord *traceData) const
     {
-        typedef typeof(nextBiggerType((Element)0)) BigElement;
+        typedef typename bigger_type_t<Element>::type BigElement;
         Fault fault = NoFault;
         %(op_decl)s;
         %(op_rd)s;

src/arch/arm/linux/atag.hh

@@ -51,7 +51,7 @@ enum {
     RevTag    = 0x54410007,
     SerialTag = 0x54410006,
     CmdTag    = 0x54410009,
-    NoneTag   = 0x00000000,
+    NoneTag   = 0x00000000
 };
 
 class AtagHeader

src/arch/arm/miscregs.cc

@@ -499,4 +499,4 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
     return NUM_MISCREGS;
 }
 
-};
+}

src/arch/arm/miscregs.hh

@@ -529,6 +529,6 @@ namespace ArmISA
       Bitfield<31>    l2rstDISABLE_monitor;
    EndBitUnion(L2CTLR)
 
-};
+}
 
 #endif // __ARCH_ARM_MISCREGS_HH__

src/arch/arm/nativetrace.cc

@@ -226,4 +226,4 @@ Trace::ArmNativeTrace *
 ArmNativeTraceParams::create()
 {
     return new Trace::ArmNativeTrace(this);
-};
+}

src/arch/arm/pagetable.hh

@@ -208,6 +208,6 @@ struct TlbEntry
 
 
 
-};
+}
 #endif // __ARCH_ARM_PAGETABLE_H__
 

src/arch/arm/predecoder.hh

@@ -149,6 +149,6 @@ namespace ArmISA
             return thisEmi;
         }
     };
-};
+}
 
 #endif // __ARCH_ARM_PREDECODER_HH__

src/arch/arm/table_walker.hh

@@ -325,7 +325,7 @@ class TableWalker : public MemObject
 
     /** Queue of requests that have passed are waiting because the walker is
      * currently busy. */
-    std::list<WalkerState *> pendingQueue;;
+    std::list<WalkerState *> pendingQueue;
 
 
     /** Port to issue translation requests from */

src/arch/arm/utility.hh

@@ -182,6 +182,6 @@ getExecutingAsid(ThreadContext *tc)
     return tc->readMiscReg(MISCREG_CONTEXTIDR);
 }
 
-};
+}
 
 #endif

src/arch/arm/vtophys.hh

@@ -45,7 +45,7 @@ namespace ArmISA {
     Addr vtophys(Addr vaddr);
     Addr vtophys(ThreadContext *tc, Addr vaddr);
     bool virtvalid(ThreadContext *tc, Addr vaddr);
-};
+}
 
 #endif // __ARCH_ARM_VTOPHYS_H__
 

src/arch/x86/bios/e820.hh

@@ -77,6 +77,6 @@ namespace X86ISA
 
         void writeTo(PortProxy& proxy, Addr countAddr, Addr addr);
     };
-};
+}
 
 #endif // __ARCH_X86_BIOS_E820_HH__

src/arch/x86/emulenv.hh

@@ -71,6 +71,6 @@ namespace X86ISA
         void doModRM(const ExtMachInst & machInst);
         void setSeg(const ExtMachInst & machInst);
     };
-};
+}
 
 #endif // __ARCH_X86_TYPES_HH__

src/arch/x86/faults.hh

@@ -419,6 +419,6 @@ namespace X86ISA
             return true;
         }
     };
-};
+}
 
 #endif // __ARCH_X86_FAULTS_HH__

src/arch/x86/isa/macroop.isa

@@ -89,7 +89,7 @@ def template MacroDeclare {{
                 std::string
                 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
             };
-        };
+        }
 }};
 
 def template MacroDisassembly {{

src/arch/x86/isa_traits.hh

@@ -85,6 +85,6 @@ namespace X86ISA
         SixtyFourBitMode                // Behave as if we're in 64 bit
                                         // mode (this doesn't actually matter).
     };
-};
+}
 
 #endif // __ARCH_X86_ISATRAITS_HH__

src/arch/x86/locked_mem.hh

@@ -53,6 +53,6 @@ namespace X86ISA
     {
         return true;
     }
-};
+}
 
 #endif // __ARCH_X86_LOCKEDMEM_HH__

src/arch/x86/mmapped_ipr.hh

@@ -78,6 +78,6 @@ namespace X86ISA
         xc->setMiscReg(index, gtoh(data));
         return xc->getCpuPtr()->ticks(1);
     }
-};
+}
 
 #endif // __ARCH_X86_MMAPPEDIPR_HH__

src/arch/x86/nativetrace.cc

@@ -197,4 +197,4 @@ Trace::X86NativeTrace *
 X86NativeTraceParams::create()
 {
     return new Trace::X86NativeTrace(this);
-};
+}

src/arch/x86/predecoder.hh

@@ -234,6 +234,6 @@ namespace X86ISA
             return emi;
         }
     };
-};
+}
 
 #endif // __ARCH_X86_PREDECODER_HH__

src/arch/x86/regs/float.hh

@@ -150,6 +150,6 @@ namespace X86ISA
     {
         return FLOATREG_FPR((top + index + 8) % 8);
     }
-};
+}
 
 #endif // __ARCH_X86_FLOATREGS_HH__

src/arch/x86/regs/int.hh

@@ -178,6 +178,6 @@ namespace X86ISA
             index = (index - 4) | foldBit;
         return (IntRegIndex)index;
     }
-};
+}
 
 #endif // __ARCH_X86_INTREGS_HH__

src/arch/x86/regs/misc.hh

@@ -915,6 +915,6 @@ namespace X86ISA
         Bitfield<11> enable;
         Bitfield<8> bsp;
     EndBitUnion(LocalApicBase)
-};
+}
 
 #endif // __ARCH_X86_INTREGS_HH__

src/arch/x86/regs/segment.hh

@@ -63,6 +63,6 @@ namespace X86ISA
 
         NUM_SEGMENTREGS
     };
-};
+}
 
 #endif // __ARCH_X86_SEGMENTREGS_HH__

src/arch/x86/tlb.cc

@@ -384,7 +384,7 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
         }
     }
     return NoFault;
-};
+}
 
 Fault
 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)

src/arch/x86/types.hh

@@ -278,7 +278,7 @@ namespace X86ISA
         }
     };
 
-};
+}
 
 namespace __hash_namespace {
     template<>

src/arch/x86/utility.hh

@@ -105,6 +105,6 @@ namespace X86ISA
         return 0;
     }
 
-};
+}
 
 #endif // __ARCH_X86_UTILITY_HH__

src/arch/x86/vtophys.hh

@@ -50,6 +50,6 @@ namespace X86ISA
 Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 
-};
+}
 
 #endif // __ARCH_X86_VTOPHYS_HH__