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Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.

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They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
This commit is contained in:
Kevin Lim
2006-02-27 11:44:35 -05:00
parent 51647e7bec
commit 70b35bab57
24 changed files with 273 additions and 642 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
cpu/exec_context.hh
View File

@@ -71,6 +71,7 @@ class ExecContext
typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
public:
enum Status
{
@@ -270,8 +271,8 @@ class ExecContext
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
MiscRegFile *cregs = &req->xc->regs.miscRegs;
cregs->lock_addr = req->paddr;
cregs->lock_flag = true;
cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
cregs->setReg(TheISA::Lock_Flag_DepTag, true);
}
#endif
@@ -297,10 +298,12 @@ class ExecContext
req->result = 2;
req->xc->storeCondFailures = 0;//Needed? [RGD]
} else {
req->result = cregs->lock_flag;
if (!cregs->lock_flag ||
((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
cregs->lock_flag = false;
bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
req->result = lock_flag;
if (!lock_flag ||
((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
cregs->setReg(TheISA::Lock_Flag_DepTag, false);
if (((++req->xc->storeCondFailures) % 100000) == 0) {
std::cerr << "Warning: "
<< req->xc->storeCondFailures
@@ -321,8 +324,9 @@ class ExecContext
// through.
for (int i = 0; i < system->execContexts.size(); i++){
cregs = &system->execContexts[i]->regs.miscRegs;
if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
cregs->lock_flag = false;
if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
(req->paddr & ~0xf)) {
cregs->setReg(TheISA::Lock_Flag_DepTag, false);
}
}
@@ -398,29 +402,27 @@ class ExecContext
regs.npc = val;
}
uint64_t readUniq()
MiscReg readMiscReg(int misc_reg)
{
return regs.miscRegs.uniq;
return regs.miscRegs.readReg(misc_reg);
}
void setUniq(uint64_t val)
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
regs.miscRegs.uniq = val;
return regs.miscRegs.readRegWithEffect(misc_reg, fault, this);
}
uint64_t readFpcr()
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
return regs.miscRegs.fpcr;
return regs.miscRegs.setReg(misc_reg, val);
}
void setFpcr(uint64_t val)
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
regs.miscRegs.fpcr = val;
return regs.miscRegs.setRegWithEffect(misc_reg, val, this);
}
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
Fault hwrei();

50
cpu/o3/alpha_cpu.hh
View File

@@ -41,6 +41,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
{
protected:
typedef TheISA::IntReg IntReg;
typedef TheISA::MiscReg MiscReg;
public:
typedef typename Impl::Params Params;
@@ -111,33 +113,24 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// Later on may want to remove this misc stuff from the regfile and
// have it handled at this level. Might prove to be an issue when
// trying to rename source/destination registers...
uint64_t readUniq()
MiscReg readMiscReg(int misc_reg)
{
return this->regFile.readUniq();
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return 0;
}
void setUniq(uint64_t val)
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
this->regFile.setUniq(val);
}
uint64_t readFpcr()
{
return this->regFile.readFpcr();
}
void setFpcr(uint64_t val)
{
this->regFile.setFpcr(val);
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return NoFault;
}
// Most of the full system code and syscall emulation is not yet
// implemented. These functions do show what the final interface will
// look like.
#if FULL_SYSTEM
uint64_t *getIpr();
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
int readIntrFlag();
void setIntrFlag(int val);
Fault hwrei();
@@ -216,8 +209,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
MiscRegFile *cregs = &req->xc->regs.miscRegs;
cregs->lock_addr = req->paddr;
cregs->lock_flag = true;
cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
cregs->setReg(TheISA::Lock_Flag_DepTag, true);
}
#endif
@@ -242,22 +235,24 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// If this is a store conditional, act appropriately
if (req->flags & LOCKED) {
cregs = &this->xc->regs.miscRegs;
cregs = &req->xc->regs.miscRegs;
if (req->flags & UNCACHEABLE) {
// Don't update result register (see stq_c in isa_desc)
req->result = 2;
req->xc->storeCondFailures = 0;//Needed? [RGD]
} else {
req->result = cregs->lock_flag;
if (!cregs->lock_flag ||
((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
cregs->lock_flag = false;
bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
req->result = lock_flag;
if (!lock_flag ||
((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
cregs->setReg(TheISA::Lock_Flag_DepTag, false);
if (((++req->xc->storeCondFailures) % 100000) == 0) {
std::cerr << "Warning: "
<< req->xc->storeCondFailures
<< " consecutive store conditional failures "
<< "on cpu " << this->cpu_id
<< "on cpu " << req->xc->cpu_id
<< std::endl;
}
return NoFault;
@@ -273,8 +268,9 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// through.
for (int i = 0; i < this->system->execContexts.size(); i++){
cregs = &this->system->execContexts[i]->regs.miscRegs;
if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
cregs->lock_flag = false;
if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
(req->paddr & ~0xf)) {
cregs->setReg(TheISA::Lock_Flag_DepTag, false);
}
}

46
cpu/o3/alpha_cpu_impl.hh
View File

@@ -179,12 +179,12 @@ AlphaFullCPU<Impl>::copyToXC()
this->xc->regs.floatRegFile.q[i] =
this->regFile.readFloatRegInt(renamed_reg);
}
/*
this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
*/
this->xc->regs.pc = this->rob.readHeadPC();
this->xc->regs.npc = this->xc->regs.pc+4;
@@ -221,13 +221,13 @@ AlphaFullCPU<Impl>::copyFromXC()
this->regFile.setFloatRegInt(renamed_reg,
this->xc->regs.floatRegFile.q[i]);
}
/*
// Then loop through the misc registers.
this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr;
this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq;
this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag;
this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr;
*/
// Then finally set the PC and the next PC.
// regFile.pc = xc->regs.pc;
// regFile.npc = xc->regs.npc;
@@ -237,27 +237,6 @@ AlphaFullCPU<Impl>::copyFromXC()
#if FULL_SYSTEM
template <class Impl>
uint64_t *
AlphaFullCPU<Impl>::getIpr()
{
return this->regFile.getIpr();
}
template <class Impl>
uint64_t
AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
{
return this->regFile.readIpr(idx, fault);
}
template <class Impl>
Fault
AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
{
return this->regFile.setIpr(idx, val);
}
template <class Impl>
int
AlphaFullCPU<Impl>::readIntrFlag()
@@ -277,16 +256,14 @@ template <class Impl>
Fault
AlphaFullCPU<Impl>::hwrei()
{
uint64_t *ipr = getIpr();
if (!inPalMode())
return UnimplementedOpcodeFault;
this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
// kernelStats.hwrei();
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
// AlphaISA::swap_palshadow(&regs, false);
this->checkInterrupts = true;
@@ -337,22 +314,23 @@ AlphaFullCPU<Impl>::trap(Fault fault)
if (fault == ArithmeticFault)
panic("Arithmetic traps are unimplemented!");
AlphaISA::InternalProcReg *ipr = getIpr();
// exception restart address - Get the commit PC
if (fault != InterruptFault || !inPalMode(PC))
ipr[AlphaISA::IPR_EXC_ADDR] = PC;
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
if (fault == PalFault || fault == ArithmeticFault /* ||
fault == InterruptFault && !PC_PAL(regs.pc) */) {
// traps... skip faulting instruction
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
AlphaISA::MiscReg ipr_exc_addr =
this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR,
ipr_exc_addr + 4);
}
if (!inPalMode(PC))
swapPALShadow(true);
this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
AlphaISA::fault_addr(fault) );
this->regFile.setNextPC(PC + sizeof(MachInst));
}

34
cpu/o3/alpha_dyn_inst.hh
View File

@@ -54,6 +54,8 @@ class AlphaDynInst : public BaseDynInst<Impl>
typedef TheISA::RegIndex RegIndex;
/** Integer register index type. */
typedef TheISA::IntReg IntReg;
/** Misc register index type. */
typedef TheISA::MiscReg MiscReg;
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
@@ -75,15 +77,35 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
public:
uint64_t readUniq();
void setUniq(uint64_t val);
MiscReg readMiscReg(int misc_reg)
{
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return 0;
}
uint64_t readFpcr();
void setFpcr(uint64_t val);
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return 0;
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return NoFault;
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return NoFault;
}
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
Fault hwrei();
int readIntrFlag();
void setIntrFlag(int val);

42
cpu/o3/alpha_dyn_inst_impl.hh
View File

@@ -67,49 +67,7 @@ AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
}
}
template <class Impl>
uint64_t
AlphaDynInst<Impl>::readUniq()
{
return this->cpu->readUniq();
}
template <class Impl>
void
AlphaDynInst<Impl>::setUniq(uint64_t val)
{
this->cpu->setUniq(val);
}
template <class Impl>
uint64_t
AlphaDynInst<Impl>::readFpcr()
{
return this->cpu->readFpcr();
}
template <class Impl>
void
AlphaDynInst<Impl>::setFpcr(uint64_t val)
{
this->cpu->setFpcr(val);
}
#if FULL_SYSTEM
template <class Impl>
uint64_t
AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
{
return this->cpu->readIpr(idx, fault);
}
template <class Impl>
Fault
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
{
return this->cpu->setIpr(idx, val);
}
template <class Impl>
Fault
AlphaDynInst<Impl>::hwrei()

4
cpu/o3/cpu.cc
View File

@@ -264,13 +264,13 @@ FullO3CPU<Impl>::init()
regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
}
/*
// Then loop through the misc registers.
regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr;
regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq;
regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag;
regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr;
*/
// Then finally set the PC and the next PC.
regFile.pc = src_xc->regs.pc;
regFile.npc = src_xc->regs.npc;

4
cpu/o3/cpu.hh
View File

@@ -152,11 +152,11 @@ class FullO3CPU : public BaseFullCPU
/** Get instruction asid. */
int getInstAsid()
{ return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); }
{ return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); }
/** Get data asid. */
int getDataAsid()
{ return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); }
{ return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); }
#else
bool validInstAddr(Addr addr)
{ return thread[0]->validInstAddr(addr); }

391
cpu/o3/regfile.hh
View File

@@ -56,6 +56,8 @@ class PhysRegFile
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
//Note that most of the definitions of the IntReg, FloatReg, etc. exist
//within the Impl/ISA class and not within this PhysRegFile class.
@@ -194,30 +196,21 @@ class PhysRegFile
//Consider leaving this stuff and below in some implementation specific
//file as opposed to the general register file. Or have a derived class.
uint64_t readUniq()
MiscReg readMiscReg(int misc_reg)
{
return miscRegs.uniq;
// Dummy function for now.
// @todo: Fix this once proxy XC is used.
return 0;
}
void setUniq(uint64_t val)
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
miscRegs.uniq = val;
}
uint64_t readFpcr()
{
return miscRegs.fpcr;
}
void setFpcr(uint64_t val)
{
miscRegs.fpcr = val;
// Dummy function for now.
// @todo: Fix this once proxy XC is used.
return NoFault;
}
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
InternalProcReg *getIpr() { return ipr; }
int readIntrFlag() { return intrflag; }
void setIntrFlag(int val) { intrflag = val; }
#endif
@@ -272,368 +265,4 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
memset(floatRegFile, 0, sizeof(*floatRegFile));
}
#if FULL_SYSTEM
//Problem: This code doesn't make sense at the RegFile level because it
//needs things such as the itb and dtb. Either put it at the CPU level or
//the DynInst level.
template <class Impl>
uint64_t
PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
{
uint64_t retval = 0; // return value, default 0
switch (idx) {
case TheISA::IPR_PALtemp0:
case TheISA::IPR_PALtemp1:
case TheISA::IPR_PALtemp2:
case TheISA::IPR_PALtemp3:
case TheISA::IPR_PALtemp4:
case TheISA::IPR_PALtemp5:
case TheISA::IPR_PALtemp6:
case TheISA::IPR_PALtemp7:
case TheISA::IPR_PALtemp8:
case TheISA::IPR_PALtemp9:
case TheISA::IPR_PALtemp10:
case TheISA::IPR_PALtemp11:
case TheISA::IPR_PALtemp12:
case TheISA::IPR_PALtemp13:
case TheISA::IPR_PALtemp14:
case TheISA::IPR_PALtemp15:
case TheISA::IPR_PALtemp16:
case TheISA::IPR_PALtemp17:
case TheISA::IPR_PALtemp18:
case TheISA::IPR_PALtemp19:
case TheISA::IPR_PALtemp20:
case TheISA::IPR_PALtemp21:
case TheISA::IPR_PALtemp22:
case TheISA::IPR_PALtemp23:
case TheISA::IPR_PAL_BASE:
case TheISA::IPR_IVPTBR:
case TheISA::IPR_DC_MODE:
case TheISA::IPR_MAF_MODE:
case TheISA::IPR_ISR:
case TheISA::IPR_EXC_ADDR:
case TheISA::IPR_IC_PERR_STAT:
case TheISA::IPR_DC_PERR_STAT:
case TheISA::IPR_MCSR:
case TheISA::IPR_ASTRR:
case TheISA::IPR_ASTER:
case TheISA::IPR_SIRR:
case TheISA::IPR_ICSR:
case TheISA::IPR_ICM:
case TheISA::IPR_DTB_CM:
case TheISA::IPR_IPLR:
case TheISA::IPR_INTID:
case TheISA::IPR_PMCTR:
// no side-effect
retval = ipr[idx];
break;
case TheISA::IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
retval |= curTick & ULL(0x00000000ffffffff);
break;
case TheISA::IPR_VA:
retval = ipr[idx];
break;
case TheISA::IPR_VA_FORM:
case TheISA::IPR_MM_STAT:
case TheISA::IPR_IFAULT_VA_FORM:
case TheISA::IPR_EXC_MASK:
case TheISA::IPR_EXC_SUM:
retval = ipr[idx];
break;
case TheISA::IPR_DTB_PTE:
{
TheISA::PTE &pte = cpu->dtb->index(1);
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
}
break;
// write only registers
case TheISA::IPR_HWINT_CLR:
case TheISA::IPR_SL_XMIT:
case TheISA::IPR_DC_FLUSH:
case TheISA::IPR_IC_FLUSH:
case TheISA::IPR_ALT_MODE:
case TheISA::IPR_DTB_IA:
case TheISA::IPR_DTB_IAP:
case TheISA::IPR_ITB_IA:
case TheISA::IPR_ITB_IAP:
fault = UnimplementedOpcodeFault;
break;
default:
// invalid IPR
fault = UnimplementedOpcodeFault;
break;
}
return retval;
}
extern int break_ipl;
template <class Impl>
Fault
PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
{
uint64_t old;
switch (idx) {
case TheISA::IPR_PALtemp0:
case TheISA::IPR_PALtemp1:
case TheISA::IPR_PALtemp2:
case TheISA::IPR_PALtemp3:
case TheISA::IPR_PALtemp4:
case TheISA::IPR_PALtemp5:
case TheISA::IPR_PALtemp6:
case TheISA::IPR_PALtemp7:
case TheISA::IPR_PALtemp8:
case TheISA::IPR_PALtemp9:
case TheISA::IPR_PALtemp10:
case TheISA::IPR_PALtemp11:
case TheISA::IPR_PALtemp12:
case TheISA::IPR_PALtemp13:
case TheISA::IPR_PALtemp14:
case TheISA::IPR_PALtemp15:
case TheISA::IPR_PALtemp16:
case TheISA::IPR_PALtemp17:
case TheISA::IPR_PALtemp18:
case TheISA::IPR_PALtemp19:
case TheISA::IPR_PALtemp20:
case TheISA::IPR_PALtemp21:
case TheISA::IPR_PALtemp22:
case TheISA::IPR_PAL_BASE:
case TheISA::IPR_IC_PERR_STAT:
case TheISA::IPR_DC_PERR_STAT:
case TheISA::IPR_PMCTR:
// write entire quad w/ no side-effect
ipr[idx] = val;
break;
case TheISA::IPR_CC_CTL:
// This IPR resets the cycle counter. We assume this only
// happens once... let's verify that.
assert(ipr[idx] == 0);
ipr[idx] = 1;
break;
case TheISA::IPR_CC:
// This IPR only writes the upper 64 bits. It's ok to write
// all 64 here since we mask out the lower 32 in rpcc (see
// isa_desc).
ipr[idx] = val;
break;
case TheISA::IPR_PALtemp23:
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
break;
case TheISA::IPR_DTB_PTE:
// write entire quad w/ no side-effect, tag is forthcoming
ipr[idx] = val;
break;
case TheISA::IPR_EXC_ADDR:
// second least significant bit in PC is always zero
ipr[idx] = val & ~2;
break;
case TheISA::IPR_ASTRR:
case TheISA::IPR_ASTER:
// only write least significant four bits - privilege mask
ipr[idx] = val & 0xf;
break;
case TheISA::IPR_IPLR:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
break;
case TheISA::IPR_DTB_CM:
case TheISA::IPR_ICM:
// only write two mode bits - processor mode
ipr[idx] = val & 0x18;
break;
case TheISA::IPR_ALT_MODE:
// only write two mode bits - processor mode
ipr[idx] = val & 0x18;
break;
case TheISA::IPR_MCSR:
// more here after optimization...
ipr[idx] = val;
break;
case TheISA::IPR_SIRR:
// only write software interrupt mask
ipr[idx] = val & 0x7fff0;
break;
case TheISA::IPR_ICSR:
ipr[idx] = val & ULL(0xffffff0300);
break;
case TheISA::IPR_IVPTBR:
case TheISA::IPR_MVPTBR:
ipr[idx] = val & ULL(0xffffffffc0000000);
break;
case TheISA::IPR_DC_TEST_CTL:
ipr[idx] = val & 0x1ffb;
break;
case TheISA::IPR_DC_MODE:
case TheISA::IPR_MAF_MODE:
ipr[idx] = val & 0x3f;
break;
case TheISA::IPR_ITB_ASN:
ipr[idx] = val & 0x7f0;
break;
case TheISA::IPR_DTB_ASN:
ipr[idx] = val & ULL(0xfe00000000000000);
break;
case TheISA::IPR_EXC_SUM:
case TheISA::IPR_EXC_MASK:
// any write to this register clears it
ipr[idx] = 0;
break;
case TheISA::IPR_INTID:
case TheISA::IPR_SL_RCV:
case TheISA::IPR_MM_STAT:
case TheISA::IPR_ITB_PTE_TEMP:
case TheISA::IPR_DTB_PTE_TEMP:
// read-only registers
return UnimplementedOpcodeFault;
case TheISA::IPR_HWINT_CLR:
case TheISA::IPR_SL_XMIT:
case TheISA::IPR_DC_FLUSH:
case TheISA::IPR_IC_FLUSH:
// the following are write only
ipr[idx] = val;
break;
case TheISA::IPR_DTB_IA:
// really a control write
ipr[idx] = 0;
cpu->dtb->flushAll();
break;
case TheISA::IPR_DTB_IAP:
// really a control write
ipr[idx] = 0;
cpu->dtb->flushProcesses();
break;
case TheISA::IPR_DTB_IS:
// really a control write
ipr[idx] = val;
cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
break;
case TheISA::IPR_DTB_TAG: {
struct TheISA::PTE pte;
// FIXME: granularity hints NYI...
if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
cpu->dtb->insert(val, pte);
}
break;
case TheISA::IPR_ITB_PTE: {
struct TheISA::PTE pte;
// FIXME: granularity hints NYI...
if (ITB_PTE_GH(val) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
pte.ppn = ITB_PTE_PPN(val);
pte.xre = ITB_PTE_XRE(val);
pte.xwe = 0;
pte.fonr = ITB_PTE_FONR(val);
pte.fonw = ITB_PTE_FONW(val);
pte.asma = ITB_PTE_ASMA(val);
pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
}
break;
case TheISA::IPR_ITB_IA:
// really a control write
ipr[idx] = 0;
cpu->itb->flushAll();
break;
case TheISA::IPR_ITB_IAP:
// really a control write
ipr[idx] = 0;
cpu->itb->flushProcesses();
break;
case TheISA::IPR_ITB_IS:
// really a control write
ipr[idx] = val;
cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
break;
default:
// invalid IPR
return UnimplementedOpcodeFault;
}
// no error...
return NoFault;
}
#endif // #if FULL_SYSTEM
#endif // __CPU_O3_CPU_REGFILE_HH__

17
cpu/simple/cpu.cc
View File

@@ -659,12 +659,11 @@ SimpleCPU::tick()
int ipl = 0;
int summary = 0;
checkInterrupts = false;
IntReg *ipr = xc->regs.ipr;
if (xc->regs.ipr[IPR_SIRR]) {
if (xc->readMiscReg(IPR_SIRR)) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
if (ipr[IPR_SIRR] & (ULL(1) << i)) {
if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
@@ -682,16 +681,16 @@ SimpleCPU::tick()
}
}
if (ipr[IPR_ASTRR])
if (xc->readMiscReg(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
ipr[IPR_ISR] = summary;
ipr[IPR_INTID] = ipl;
if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) {
xc->setMiscReg(IPR_ISR, summary);
xc->setMiscReg(IPR_INTID, ipl);
xc->ev5_trap(InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[IPR_IPLR], ipl, summary);
xc->readMiscReg(IPR_IPLR), ipl, summary);
}
}
#endif
@@ -782,7 +781,7 @@ SimpleCPU::tick()
}
if (xc->profile) {
bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
xc->profilePC = usermode ? 1 : xc->regs.pc;
ProfileNode *node = xc->profile->consume(xc, inst);
if (node)

25
cpu/simple/cpu.hh
View File

@@ -65,6 +65,7 @@ class SimpleCPU : public BaseCPU
{
protected:
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg;
public:
// main simulation loop (one cycle)
void tick();
@@ -321,15 +322,27 @@ class SimpleCPU : public BaseCPU
uint64_t readPC() { return xc->readPC(); }
void setNextPC(uint64_t val) { xc->setNextPC(val); }
uint64_t readUniq() { return xc->readUniq(); }
void setUniq(uint64_t val) { xc->setUniq(val); }
MiscReg readMiscReg(int misc_reg)
{
return xc->readMiscReg(misc_reg);
}
uint64_t readFpcr() { return xc->readFpcr(); }
void setFpcr(uint64_t val) { xc->setFpcr(val); }
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
return xc->readMiscRegWithEffect(misc_reg, fault);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
return xc->setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return xc->setMiscRegWithEffect(misc_reg, val);
}
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault hwrei() { return xc->hwrei(); }
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }