diff --git a/src/mem/dram_interface.cc b/src/mem/dram_interface.cc
index 65e06db4d3..fca3282f27 100644
--- a/src/mem/dram_interface.cc
+++ b/src/mem/dram_interface.cc
@@ -579,7 +579,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
         stats.readBursts++;
         if (row_hit)
             stats.readRowHits++;
-        stats.bytesRead += burstSize;
+        stats.dramBytesRead += burstSize;
         stats.perBankRdBursts[mem_pkt->bankId]++;
 
         // Update latency stats
@@ -608,7 +608,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
         stats.writeBursts++;
         if (row_hit)
             stats.writeRowHits++;
-        stats.bytesWritten += burstSize;
+        stats.dramBytesWritten += burstSize;
         stats.perBankWrBursts[mem_pkt->bankId]++;
 
     }
@@ -1885,9 +1885,9 @@ DRAMInterface::DRAMStats::DRAMStats(DRAMInterface &_dram)
 
     ADD_STAT(bytesPerActivate, statistics::units::Byte::get(),
              "Bytes accessed per row activation"),
-    ADD_STAT(bytesRead, statistics::units::Byte::get(),
+    ADD_STAT(dramBytesRead, statistics::units::Byte::get(),
             "Total bytes read"),
-    ADD_STAT(bytesWritten, statistics::units::Byte::get(),
+    ADD_STAT(dramBytesWritten, statistics::units::Byte::get(),
             "Total bytes written"),
 
     ADD_STAT(avgRdBW, statistics::units::Rate<
@@ -1948,8 +1948,8 @@ DRAMInterface::DRAMStats::regStats()
     readRowHitRate = (readRowHits / readBursts) * 100;
     writeRowHitRate = (writeRowHits / writeBursts) * 100;
 
-    avgRdBW = (bytesRead / 1000000) / simSeconds;
-    avgWrBW = (bytesWritten / 1000000) / simSeconds;
+    avgRdBW = (dramBytesRead / 1000000) / simSeconds;
+    avgWrBW = (dramBytesWritten / 1000000) / simSeconds;
     peakBW = (sim_clock::Frequency / dram.burstDelay()) *
               dram.bytesPerBurst() / 1000000;
 
diff --git a/src/mem/dram_interface.hh b/src/mem/dram_interface.hh
index e20e33faf9..2070a1773b 100644
--- a/src/mem/dram_interface.hh
+++ b/src/mem/dram_interface.hh
@@ -610,8 +610,8 @@ class DRAMInterface : public MemInterface
         statistics::Formula writeRowHitRate;
         statistics::Histogram bytesPerActivate;
         // Number of bytes transferred to/from DRAM
-        statistics::Scalar bytesRead;
-        statistics::Scalar bytesWritten;
+        statistics::Scalar dramBytesRead;
+        statistics::Scalar dramBytesWritten;
 
         // Average bandwidth
         statistics::Formula avgRdBW;
diff --git a/src/mem/nvm_interface.cc b/src/mem/nvm_interface.cc
index 366f71d56a..d9996f0ec9 100644
--- a/src/mem/nvm_interface.cc
+++ b/src/mem/nvm_interface.cc
@@ -538,7 +538,7 @@ NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at,
     // Update the stats
     if (pkt->isRead()) {
         stats.readBursts++;
-        stats.bytesRead += burstSize;
+        stats.nvmBytesRead += burstSize;
         stats.perBankRdBursts[pkt->bankId]++;
         stats.pendingReads.sample(numPendingReads);
 
@@ -548,7 +548,7 @@ NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at,
         stats.totQLat += cmd_at - pkt->entryTime;
     } else {
         stats.writeBursts++;
-        stats.bytesWritten += burstSize;
+        stats.nvmBytesWritten += burstSize;
         stats.perBankWrBursts[pkt->bankId]++;
     }
 
@@ -650,6 +650,11 @@ NVMInterface::NVMStats::NVMStats(NVMInterface &_nvm)
                 statistics::units::Tick, statistics::units::Count>::get(),
              "Average memory access latency per NVM burst"),
 
+    ADD_STAT(nvmBytesRead, statistics::units::Byte::get(),
+            "Total bytes read"),
+    ADD_STAT(nvmBytesWritten, statistics::units::Byte::get(),
+            "Total bytes written"),
+
     ADD_STAT(avgRdBW, statistics::units::Rate<
                 statistics::units::Byte, statistics::units::Second>::get(),
              "Average DRAM read bandwidth in MiBytes/s"),
@@ -715,8 +720,8 @@ NVMInterface::NVMStats::regStats()
     avgBusLat = totBusLat / readBursts;
     avgMemAccLat = totMemAccLat / readBursts;
 
-    avgRdBW = (bytesRead / 1000000) / simSeconds;
-    avgWrBW = (bytesWritten / 1000000) / simSeconds;
+    avgRdBW = (nvmBytesRead / 1000000) / simSeconds;
+    avgWrBW = (nvmBytesWritten / 1000000) / simSeconds;
     peakBW = (sim_clock::Frequency / nvm.tBURST) *
               nvm.burstSize / 1000000;
 
diff --git a/src/mem/nvm_interface.hh b/src/mem/nvm_interface.hh
index cc41587fe0..547fdbb5f8 100644
--- a/src/mem/nvm_interface.hh
+++ b/src/mem/nvm_interface.hh
@@ -125,8 +125,8 @@ class NVMInterface : public MemInterface
         statistics::Formula avgBusLat;
         statistics::Formula avgMemAccLat;
 
-        statistics::Scalar bytesRead;
-        statistics::Scalar bytesWritten;
+        statistics::Scalar nvmBytesRead;
+        statistics::Scalar nvmBytesWritten;
 
         // Average bandwidth
         statistics::Formula avgRdBW;