diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index cd00f5d63a..a9ad7b1d32 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -106,6 +106,10 @@ RiscvProcess64::initState()
         tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
         auto *isa = dynamic_cast<ISA*>(tc->getIsaPtr());
         fatal_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits mode");
+        MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA);
+        fatal_if(!(misa.rvu && misa.rvs),
+            "RISC V SE mode can't run without supervisor and user "
+            "privilege modes.");
     }
 }
 
@@ -120,6 +124,10 @@ RiscvProcess32::initState()
         tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
         auto *isa = dynamic_cast<ISA*>(tc->getIsaPtr());
         fatal_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits mode");
+        MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA);
+        fatal_if(!(misa.rvu && misa.rvs),
+            "RISC V SE mode can't run without supervisor and user "
+            "privilege modes.");
     }
 }