Cache: add a response latency to the caches

In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.

src/mem/cache/BaseCache.py

@@ -36,7 +36,9 @@ class BaseCache(MemObject):
     type = 'BaseCache'
     assoc = Param.Int("associativity")
     block_size = Param.Int("block size in bytes")
-    latency = Param.Latency("Latency")
+    hit_latency = Param.Latency("The hit latency for this cache")
+    response_latency = Param.Latency(
+            "Additional cache latency for the return path to core on a miss");
     hash_delay = Param.Cycles(1, "time in cycles of hash access")
     max_miss_count = Param.Counter(0,
         "number of misses to handle before calling exit")

src/mem/cache/base.cc

@@ -69,7 +69,8 @@ BaseCache::BaseCache(const Params *p)
       writeBuffer("write buffer", p->write_buffers, p->mshrs+1000,
                   MSHRQueue_WriteBuffer),
       blkSize(p->block_size),
-      hitLatency(p->latency),
+      hitLatency(p->hit_latency),
+      responseLatency(p->response_latency),
       numTarget(p->tgts_per_mshr),
       forwardSnoops(p->forward_snoops),
       isTopLevel(p->is_top_level),

src/mem/cache/base.hh

@@ -229,7 +229,15 @@ class BaseCache : public MemObject
     /**
      * The latency of a hit in this device.
      */
-    int hitLatency;
+    const Tick hitLatency;
+
+    /**
+     * The latency of sending reponse to its upper level cache/core on a
+     * linefill. In most contemporary processors, the return path on a cache
+     * miss is much quicker that the hit latency. The responseLatency parameter
+     * tries to capture this latency.
+     */
+    const Tick responseLatency;
 
     /** The number of targets for each MSHR. */
     const int numTarget;

src/mem/cache/builder.cc

@@ -71,7 +71,7 @@ using namespace std;
 
 #if defined(USE_CACHE_FALRU)
 #define BUILD_FALRU_CACHE do {                              \
-        FALRU *tags = new FALRU(block_size, size, latency); \
+        FALRU *tags = new FALRU(block_size, size, hit_latency); \
         BUILD_CACHE(FALRU, tags);                           \
     } while (0)
 #else
@@ -80,7 +80,7 @@ using namespace std;
 
 #if defined(USE_CACHE_LRU)
 #define BUILD_LRU_CACHE do {                                            \
-        LRU *tags = new LRU(numSets, block_size, assoc, latency);       \
+        LRU *tags = new LRU(numSets, block_size, assoc, hit_latency);       \
         BUILD_CACHE(LRU, tags);                                         \
     } while (0)
 #else
@@ -124,7 +124,7 @@ BaseCacheParams::create()
     iic_params.blkSize = block_size;
     iic_params.assoc = assoc;
     iic_params.hashDelay = hash_delay;
-    iic_params.hitLatency = latency;
+    iic_params.hitLatency = hit_latency;
     iic_params.rp = repl;
     iic_params.subblockSize = subblock_size;
 #else

src/mem/cache/cache_impl.hh

@@ -897,8 +897,11 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
                     transfer_offset += blkSize;
                 }
 
-                // If critical word (no offset) return first word time
-                completion_time = tags->getHitLatency() +
+                // If critical word (no offset) return first word time.
+                // responseLatency is the latency of the return path
+                // from lower level caches/memory to an upper level cache or
+                // the core.
+                completion_time = responseLatency +
                     (transfer_offset ? pkt->finishTime : pkt->firstWordTime);
 
                 assert(!target->pkt->req->isUncacheable());
@@ -911,11 +914,16 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
                 assert(target->pkt->cmd == MemCmd::StoreCondReq ||
                        target->pkt->cmd == MemCmd::StoreCondFailReq ||
                        target->pkt->cmd == MemCmd::SCUpgradeFailReq);
-                completion_time = tags->getHitLatency() + pkt->finishTime;
+                // responseLatency is the latency of the return path
+                // from lower level caches/memory to an upper level cache or
+                // the core.
+                completion_time = responseLatency + pkt->finishTime;
                 target->pkt->req->setExtraData(0);
             } else {
                 // not a cache fill, just forwarding response
-                completion_time = tags->getHitLatency() + pkt->finishTime;
+                // responseLatency is the latency of the return path
+                // from lower level cahces/memory to the core.
+                completion_time = responseLatency + pkt->finishTime;
                 if (pkt->isRead() && !is_error) {
                     target->pkt->setData(pkt->getPtr<uint8_t>());
                 }