From 6f3c19774224c1b77b2f1120fd550bb6b360c0aa Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 23 Feb 2021 17:49:15 -0800 Subject: [PATCH] cpu: Eliminate the isZeroReg() helper in RegId. The isZeroReg() helper checked if the register was both an integer register, and if it equaled TheISA::ZeroReg. This bakes in both the assumption that any zero registers are integer (and that integer registers are a thing), and also internalizes the plumbing which selects what index is the zero register. This change eliminates the isZeroReg helper and moves the logic inside it into where it was called. In most cases, it was actually not necessary to check if the register was integer since that was already implied by context. This also brings the TheISA::ZeroReg constant out, where it can be replaced by values plumbed in more generally than a fixed, ISA specific constant. Change-Id: I651762b6eb01fea83ec0b0076e8be9bf24b5b0da Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42683 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/cpu/minor/dyn_inst.cc | 2 +- src/cpu/minor/scoreboard.cc | 62 +++++++++++++++---------------- src/cpu/o3/probe/elastic_trace.cc | 5 ++- src/cpu/o3/regfile.hh | 5 +-- src/cpu/o3/rename_map.cc | 2 +- src/cpu/o3/scoreboard.hh | 13 ++++--- src/cpu/reg_class.hh | 13 ------- 7 files changed, 45 insertions(+), 57 deletions(-) diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc index 1e34a88095..ceac89446a 100644 --- a/src/cpu/minor/dyn_inst.cc +++ b/src/cpu/minor/dyn_inst.cc @@ -164,7 +164,7 @@ printRegName(std::ostream &os, const RegId& reg) static_cast(reg.elemIndex()) << ']'; break; case IntRegClass: - if (reg.isZeroReg()) { + if (reg.index() == TheISA::ZeroReg) { os << 'z'; } else { os << 'r' << static_cast(reg.index()); diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc index 0d943f1b63..5f8df8766d 100644 --- a/src/cpu/minor/scoreboard.cc +++ b/src/cpu/minor/scoreboard.cc @@ -50,41 +50,39 @@ Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index) { bool ret = false; - if (reg.isZeroReg()) { - /* Don't bother with the zero register */ - ret = false; - } else { - switch (reg.classValue()) - { - case IntRegClass: + switch (reg.classValue()) { + case IntRegClass: + if (reg.index() == TheISA::ZeroReg) { + /* Don't bother with the zero register */ + ret = false; + } else { scoreboard_index = reg.index(); ret = true; - break; - case FloatRegClass: - scoreboard_index = floatRegOffset + reg.index(); - ret = true; - break; - case VecRegClass: - case VecElemClass: - scoreboard_index = vecRegOffset + reg.index(); - ret = true; - break; - case VecPredRegClass: - scoreboard_index = vecPredRegOffset + reg.index(); - ret = true; - break; - case CCRegClass: - scoreboard_index = ccRegOffset + reg.index(); - ret = true; - break; - case MiscRegClass: - /* Don't bother with Misc registers */ - ret = false; - break; - default: - panic("Unknown register class: %d", - static_cast(reg.classValue())); } + break; + case FloatRegClass: + scoreboard_index = floatRegOffset + reg.index(); + ret = true; + break; + case VecRegClass: + case VecElemClass: + scoreboard_index = vecRegOffset + reg.index(); + ret = true; + break; + case VecPredRegClass: + scoreboard_index = vecPredRegOffset + reg.index(); + ret = true; + break; + case CCRegClass: + scoreboard_index = ccRegOffset + reg.index(); + ret = true; + break; + case MiscRegClass: + /* Don't bother with Misc registers */ + ret = false; + break; + default: + panic("Unknown register class: %d", reg.classValue()); } return ret; diff --git a/src/cpu/o3/probe/elastic_trace.cc b/src/cpu/o3/probe/elastic_trace.cc index ddea0411bf..b48504abdf 100644 --- a/src/cpu/o3/probe/elastic_trace.cc +++ b/src/cpu/o3/probe/elastic_trace.cc @@ -241,7 +241,7 @@ ElasticTrace::updateRegDep(const DynInstConstPtr& dyn_inst) const RegId& src_reg = dyn_inst->srcRegIdx(src_idx); if (!src_reg.isMiscReg() && - !src_reg.isZeroReg()) { + !(src_reg.isIntReg() && src_reg.index() == TheISA::ZeroReg)) { // Get the physical register index of the i'th source register. PhysRegIdPtr phys_src_reg = dyn_inst->regs.renamedSrcIdx(src_idx); DPRINTFR(ElasticTrace, "[sn:%lli] Check map for src reg" @@ -273,7 +273,8 @@ ElasticTrace::updateRegDep(const DynInstConstPtr& dyn_inst) // CC register and not a Misc register. const RegId& dest_reg = dyn_inst->destRegIdx(dest_idx); if (!dest_reg.isMiscReg() && - !dest_reg.isZeroReg()) { + !(dest_reg.isIntReg() && + dest_reg.index() == TheISA::ZeroReg)) { // Get the physical register index of the i'th destination // register. PhysRegIdPtr phys_dest_reg = diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 8b45d61926..63f7f3cb3a 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -274,7 +274,7 @@ class PhysRegFile DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", phys_reg->index(), val); - if (!phys_reg->isZeroReg()) + if (phys_reg->index() != TheISA::ZeroReg) intRegFile[phys_reg->index()] = val; } @@ -286,8 +286,7 @@ class PhysRegFile DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", phys_reg->index(), (uint64_t)val); - if (!phys_reg->isZeroReg()) - floatRegFile[phys_reg->index()] = val; + floatRegFile[phys_reg->index()] = val; } /** Sets a vector register to the given value. */ diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc index 8046be72c7..88199c2dcf 100644 --- a/src/cpu/o3/rename_map.cc +++ b/src/cpu/o3/rename_map.cc @@ -76,7 +76,7 @@ SimpleRenameMap::rename(const RegId& arch_reg) PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()]; if (arch_reg == zeroReg) { - assert(prev_reg->isZeroReg()); + assert(prev_reg->index() == TheISA::ZeroReg); renamed_reg = prev_reg; } else if (prev_reg->getNumPinnedWrites() > 0) { // Do not rename if the register is pinned diff --git a/src/cpu/o3/scoreboard.hh b/src/cpu/o3/scoreboard.hh index 0a37b40617..18731165bf 100644 --- a/src/cpu/o3/scoreboard.hh +++ b/src/cpu/o3/scoreboard.hh @@ -72,7 +72,8 @@ class Scoreboard std::string name() const { return _name; }; /** Checks if the register is ready. */ - bool getReg(PhysRegIdPtr phys_reg) const + bool + getReg(PhysRegIdPtr phys_reg) const { assert(phys_reg->flatIndex() < numPhysRegs); @@ -83,14 +84,15 @@ class Scoreboard bool ready = regScoreBoard[phys_reg->flatIndex()]; - if (phys_reg->isZeroReg()) + if (phys_reg->isIntPhysReg() && phys_reg->index() == TheISA::ZeroReg) assert(ready); return ready; } /** Sets the register as ready. */ - void setReg(PhysRegIdPtr phys_reg) + void + setReg(PhysRegIdPtr phys_reg) { assert(phys_reg->flatIndex() < numPhysRegs); @@ -107,7 +109,8 @@ class Scoreboard } /** Sets the register as not ready. */ - void unsetReg(PhysRegIdPtr phys_reg) + void + unsetReg(PhysRegIdPtr phys_reg) { assert(phys_reg->flatIndex() < numPhysRegs); @@ -118,7 +121,7 @@ class Scoreboard } // zero reg should never be marked unready - if (phys_reg->isZeroReg()) + if (phys_reg->isIntPhysReg() && phys_reg->index() == TheISA::ZeroReg) return; regScoreBoard[phys_reg->flatIndex()] = false; diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh index 231cdc3fd6..84b513c9c9 100644 --- a/src/cpu/reg_class.hh +++ b/src/cpu/reg_class.hh @@ -145,18 +145,6 @@ class RegId return regClass != MiscRegClass; } - /** - * Check if this is the zero register. - * Returns true if this register is a zero register (needs to have a - * constant zero value throughout the execution). - */ - - inline bool - isZeroReg() const - { - return regClass == IntRegClass && regIdx == TheISA::ZeroReg; - } - /** @return true if it is an integer physical register. */ bool isIntReg() const { return regClass == IntRegClass; } @@ -262,7 +250,6 @@ class PhysRegId : private RegId /** @{ */ using RegId::index; using RegId::classValue; - using RegId::isZeroReg; using RegId::className; using RegId::elemIndex; /** @} */