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Replace curTick global variable with accessor functions.

Browse Source 
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
This commit is contained in:
Steve Reinhardt
2011-01-07 21:50:29 -08:00
parent c22be9f2f0
commit 6f1187943c
129 changed files with 515 additions and 509 deletions
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28
src/cpu/inorder/cpu.cc
View File

@@ -158,7 +158,7 @@ void
InOrderCPU::CPUEvent::scheduleEvent(int delay)
{
assert(!scheduled() || squashed());
cpu->reschedule(this, cpu->nextCycle(curTick + cpu->ticks(delay)), true);
cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
}
void
@@ -337,7 +337,7 @@ InOrderCPU::InOrderCPU(Params *params)
dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyBufferInst->setSquashed();
lastRunningCycle = curTick;
lastRunningCycle = curTick();
// Reset CPU to reset state.
#if FULL_SYSTEM
@@ -528,17 +528,17 @@ InOrderCPU::tick()
if (!tickEvent.scheduled()) {
if (_status == SwitchedOut) {
// increment stat
lastRunningCycle = curTick;
lastRunningCycle = curTick();
} else if (!activityRec.active()) {
DPRINTF(InOrderCPU, "sleeping CPU.\n");
lastRunningCycle = curTick;
lastRunningCycle = curTick();
timesIdled++;
} else {
//Tick next_tick = curTick + cycles(1);
//Tick next_tick = curTick() + cycles(1);
//tickEvent.schedule(next_tick);
schedule(&tickEvent, nextCycle(curTick + 1));
schedule(&tickEvent, nextCycle(curTick() + 1));
DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
nextCycle(curTick + 1));
nextCycle(curTick() + 1));
}
}
@@ -693,10 +693,10 @@ InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
event_pri_offset);
Tick sked_tick = nextCycle(curTick + ticks(delay));
Tick sked_tick = nextCycle(curTick() + ticks(delay));
if (delay >= 0) {
DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
eventNames[c_event], curTick + delay, tid);
eventNames[c_event], curTick() + delay, tid);
schedule(cpu_event, sked_tick);
} else {
cpu_event->process();
@@ -791,7 +791,7 @@ InOrderCPU::activateThread(ThreadID tid)
activateThreadInPipeline(tid);
thread[tid]->lastActivate = curTick;
thread[tid]->lastActivate = curTick();
tcBase(tid)->setStatus(ThreadContext::Active);
@@ -963,7 +963,7 @@ InOrderCPU::suspendThread(ThreadID tid)
tid);
deactivateThread(tid);
suspendedThreads.push_back(tid);
thread[tid]->lastSuspend = curTick;
thread[tid]->lastSuspend = curTick();
tcBase(tid)->setStatus(ThreadContext::Suspended);
}
@@ -1124,7 +1124,7 @@ InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
// Finalize Trace Data For Instruction
if (inst->traceData) {
//inst->traceData->setCycle(curTick);
//inst->traceData->setCycle(curTick());
inst->traceData->setFetchSeq(inst->seqNum);
//inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
inst->traceData->dump();
@@ -1390,7 +1390,7 @@ InOrderCPU::wakeCPU()
DPRINTF(Activity, "Waking up CPU\n");
Tick extra_cycles = tickToCycles((curTick - 1) - lastRunningCycle);
Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
idleCycles += extra_cycles;
for (int stage_num = 0; stage_num < NumStages; stage_num++) {
@@ -1399,7 +1399,7 @@ InOrderCPU::wakeCPU()
numCycles += extra_cycles;
schedule(&tickEvent, nextCycle(curTick));
schedule(&tickEvent, nextCycle(curTick()));
}
#if FULL_SYSTEM

2
src/cpu/inorder/cpu.hh
View File

@@ -157,7 +157,7 @@ class InOrderCPU : public BaseCPU
void scheduleTickEvent(int delay)
{
assert(!tickEvent.scheduled() || tickEvent.squashed());
reschedule(&tickEvent, nextCycle(curTick + ticks(delay)), true);
reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
}
/** Unschedule tick event, regardless of its current state. */

8
src/cpu/inorder/inorder_dyn_inst.cc
View File

@@ -442,7 +442,7 @@ InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
"being set to %#x.\n", threadNumber, seqNum, idx, val);
@@ -472,7 +472,7 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
"being set to %#x (result-tick:%i).\n",
@@ -485,7 +485,7 @@ InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
instResult[idx].val.dbl = val;
instResult[idx].type = Float;
instResult[idx].tick = curTick;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
"being set to %#x (result-tick:%i).\n",
@@ -499,7 +499,7 @@ InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
"being set to %#x (result-tick:%i).\n",

10
src/cpu/inorder/pipeline_stage.cc
View File

@@ -338,7 +338,7 @@ void
PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
{
if (cpu->squashSeqNum[tid] < inst->seqNum &&
cpu->lastSquashCycle[tid] == curTick){
cpu->lastSquashCycle[tid] == curTick()){
DPRINTF(Resource, "Ignoring [sn:%i] branch squash signal due to "
"another stage's squash signal for after [sn:%i].\n",
inst->seqNum, cpu->squashSeqNum[tid]);
@@ -371,7 +371,7 @@ PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
// Save squash num for later stage use
cpu->squashSeqNum[tid] = squash_seq_num;
cpu->lastSquashCycle[tid] = curTick;
cpu->lastSquashCycle[tid] = curTick();
}
}
@@ -969,7 +969,7 @@ PipelineStage::processInstSchedule(DynInstPtr inst,int &reqs_processed)
inst->popSchedEntry();
} else {
panic("%i: encountered %s fault!\n",
curTick, req->fault->name());
curTick(), req->fault->name());
}
reqs_processed++;
@@ -1075,7 +1075,7 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
if (nextStageQueueValid(inst->nextStage - 1)) {
if (inst->seqNum > cpu->squashSeqNum[tid] &&
curTick == cpu->lastSquashCycle[tid]) {
curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, skipping "
"insertion into stage %i queue.\n", tid, inst->seqNum,
inst->nextStage);
@@ -1107,7 +1107,7 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
// Take note of trace data for this inst & stage
if (inst->traceData) {
inst->traceData->setStageCycle(stageNum, curTick);
inst->traceData->setStageCycle(stageNum, curTick());
}
}

4
src/cpu/inorder/reg_dep_map.cc
View File

@@ -181,14 +181,14 @@ RegDepMap::canForward(unsigned reg_idx, DynInstPtr inst)
assert(dest_reg_idx != -1);
if (forward_inst->isExecuted() &&
forward_inst->readResultTime(dest_reg_idx) < curTick) {
forward_inst->readResultTime(dest_reg_idx) < curTick()) {
return forward_inst;
} else {
if (!forward_inst->isExecuted()) {
DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
"forwarding, [sn:%i] has not been executed yet.\n",
inst->seqNum, forward_inst->seqNum);
} else if (forward_inst->readResultTime(dest_reg_idx) >= curTick) {
} else if (forward_inst->readResultTime(dest_reg_idx) >= curTick()) {
DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
"forwarding, [sn:%i] executed on tick:%i.\n",
inst->seqNum, forward_inst->seqNum,

4
src/cpu/inorder/resource.cc
View File

@@ -366,7 +366,7 @@ Resource::scheduleEvent(int slot_idx, int delay)
DPRINTF(Resource, "[tid:%i]: Scheduling event for [sn:%i] on tick %i.\n",
reqMap[slot_idx]->inst->readTid(),
reqMap[slot_idx]->inst->seqNum,
cpu->ticks(delay) + curTick);
cpu->ticks(delay) + curTick());
resourceEvent[slot_idx].scheduleEvent(delay);
}
@@ -504,5 +504,5 @@ ResourceEvent::scheduleEvent(int delay)
{
assert(!scheduled() || squashed());
resource->cpu->reschedule(this,
curTick + resource->ticks(delay), true);
curTick() + resource->ticks(delay), true);
}

20
src/cpu/inorder/resource_pool.9stage.cc
View File

@@ -177,13 +177,13 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case InOrderCPU::ActivateThread:
{
DPRINTF(Resource, "Scheduling Activate Thread Resource Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->bdelaySeqNum,
inst->readTid());
res_pool_event->schedule(curTick + cpu->cycles(delay));
res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
@@ -192,7 +192,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case InOrderCPU::DeallocateThread:
{
DPRINTF(Resource, "Scheduling Deactivate Thread Resource Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
@@ -200,7 +200,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
inst->bdelaySeqNum,
tid);
res_pool_event->schedule(curTick + cpu->cycles(delay));
res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
@@ -208,14 +208,14 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case ResourcePool::InstGraduated:
{
DPRINTF(Resource, "Scheduling Inst-Graduated Resource Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->seqNum,
inst->readTid());
res_pool_event->schedule(curTick + cpu->cycles(delay));
res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
@@ -223,13 +223,13 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case ResourcePool::SquashAll:
{
DPRINTF(Resource, "Scheduling Squash Resource Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->bdelaySeqNum,
inst->readTid());
res_pool_event->schedule(curTick + cpu->cycles(delay));
res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
@@ -345,9 +345,9 @@ void
ResourcePool::ResPoolEvent::scheduleEvent(int delay)
{
if (squashed())
reschedule(curTick + resPool->cpu->cycles(delay));
reschedule(curTick() + resPool->cpu->cycles(delay));
else if (!scheduled())
schedule(curTick + resPool->cpu->cycles(delay));
schedule(curTick() + resPool->cpu->cycles(delay));
}
/** Unschedule resource event, regardless of its current state. */

16
src/cpu/inorder/resource_pool.cc
View File

@@ -244,14 +244,14 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
{
assert(delay >= 0);
Tick when = cpu->nextCycle(curTick + cpu->ticks(delay));
Tick when = cpu->nextCycle(curTick() + cpu->ticks(delay));
switch (e_type)
{
case InOrderCPU::ActivateThread:
{
DPRINTF(Resource, "Scheduling Activate Thread Resource Pool Event "
"for tick %i, [tid:%i].\n", curTick + delay,
"for tick %i, [tid:%i].\n", curTick() + delay,
inst->readTid());
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,
@@ -269,7 +269,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
{
DPRINTF(Resource, "Scheduling Deactivate Thread Resource Pool "
"Event for tick %i.\n", curTick + delay);
"Event for tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,
e_type,
@@ -304,7 +304,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case ResourcePool::InstGraduated:
{
DPRINTF(Resource, "Scheduling Inst-Graduated Resource Pool "
"Event for tick %i.\n", curTick + delay);
"Event for tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
@@ -318,7 +318,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case ResourcePool::SquashAll:
{
DPRINTF(Resource, "Scheduling Squash Resource Pool Event for "
"tick %i.\n", curTick + delay);
"tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
@@ -333,7 +333,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
{
DPRINTF(Resource, "Scheduling Squash Due to Memory Stall Resource "
"Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
@@ -348,7 +348,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
{
DPRINTF(Resource, "Scheduling UpdatePC Resource Pool Event "
"for tick %i.\n",
curTick + delay);
curTick() + delay);
ResPoolEvent *res_pool_event = new ResPoolEvent(this,e_type,
inst,
inst->squashingStage,
@@ -542,7 +542,7 @@ ResourcePool::ResPoolEvent::scheduleEvent(int delay)
{
InOrderCPU *cpu = resPool->cpu;
assert(!scheduled() || squashed());
cpu->reschedule(this, cpu->nextCycle(curTick + cpu->ticks(delay)), true);
cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
}
/** Unschedule resource event, regardless of its current state. */

4
src/cpu/inorder/resources/branch_predictor.cc
View File

@@ -80,7 +80,7 @@ BranchPredictor::execute(int slot_num)
case PredictBranch:
{
if (inst->seqNum > cpu->squashSeqNum[tid] &&
curTick == cpu->lastSquashCycle[tid]) {
curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
"skipping prediction \n", tid, inst->seqNum);
} else {
@@ -125,7 +125,7 @@ BranchPredictor::execute(int slot_num)
case UpdatePredictor:
{
if (inst->seqNum > cpu->squashSeqNum[tid] &&
curTick == cpu->lastSquashCycle[tid]) {
curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
"skipping branch predictor update \n",
tid, inst->seqNum);

8
src/cpu/inorder/resources/cache_unit.cc
View File

@@ -63,7 +63,7 @@ Tick
CacheUnit::CachePort::recvAtomic(PacketPtr pkt)
{
panic("CacheUnit::CachePort doesn't expect recvAtomic callback!");
return curTick;
return curTick();
}
void
@@ -167,7 +167,7 @@ CacheUnit::getSlot(DynInstPtr inst)
if (new_slot == -1)
return -1;
inst->memTime = curTick;
inst->memTime = curTick();
setAddrDependency(inst);
return new_slot;
} else {
@@ -343,7 +343,7 @@ CacheUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
break;
default:
panic("%i: Unexpected request type (%i) to %s", curTick,
panic("%i: Unexpected request type (%i) to %s", curTick(),
sched_entry->cmd, name());
}
@@ -482,7 +482,7 @@ CacheUnit::read(DynInstPtr inst, Addr addr,
if (secondAddr > addr && !inst->split2ndAccess) {
DPRINTF(InOrderCachePort, "%i: sn[%i] Split Read Access (1 of 2) for "
"(%#x, %#x).\n", curTick, inst->seqNum, addr, secondAddr);
"(%#x, %#x).\n", curTick(), inst->seqNum, addr, secondAddr);
// Save All "Total" Split Information
// ==============================

6
src/cpu/inorder/resources/execution_unit.cc
View File

@@ -55,7 +55,7 @@ ExecutionUnit::regStats()
.name(name() + ".predictedNotTakenIncorrect")
.desc("Number of Branches Incorrectly Predicted As Not Taken).");
lastExecuteCycle = curTick;
lastExecuteCycle = curTick();
executions
.name(name() + ".executions")
@@ -98,8 +98,8 @@ ExecutionUnit::execute(int slot_num)
{
case ExecuteInst:
{
if (curTick != lastExecuteCycle) {
lastExecuteCycle = curTick;
if (curTick() != lastExecuteCycle) {
lastExecuteCycle = curTick();
}

4
src/cpu/inorder/resources/fetch_seq_unit.cc
View File

@@ -210,13 +210,13 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
}
if (squashSeqNum[tid] <= done_seq_num &&
lastSquashCycle[tid] == curTick) {
lastSquashCycle[tid] == curTick()) {
DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
"since there is an outstanding squash that is older.\n",
tid, squash_stage);
} else {
squashSeqNum[tid] = done_seq_num;
lastSquashCycle[tid] = curTick;
lastSquashCycle[tid] = curTick();
// If The very next instruction number is the done seq. num,
// then we haven't seen the delay slot yet ... if it isn't

6
src/cpu/inorder/resources/graduation_unit.cc
View File

@@ -64,8 +64,8 @@ GraduationUnit::execute(int slot_num)
// @TODO: Instructions should never really get to this point since
// this should be handled through the request interface. Check to
// make sure this happens and delete this code.
if (lastCycleGrad != curTick) {
lastCycleGrad = curTick;
if (lastCycleGrad != curTick()) {
lastCycleGrad = curTick();
numCycleGrad = 0;
} else if (numCycleGrad > width) {
DPRINTF(InOrderGraduation,
@@ -91,7 +91,7 @@ GraduationUnit::execute(int slot_num)
}
if (inst->traceData) {
inst->traceData->setStageCycle(stage_num, curTick);
inst->traceData->setStageCycle(stage_num, curTick());
}
// Tell CPU that instruction is finished processing

4
src/cpu/inorder/resources/mult_div_unit.cc
View File

@@ -163,7 +163,7 @@ MultDivUnit::getSlot(DynInstPtr inst)
}
}
if (lastMDUCycle + repeat_rate > curTick) {
if (lastMDUCycle + repeat_rate > curTick()) {
DPRINTF(InOrderMDU, "MDU not ready to process another inst. until %i, "
"denying request.\n", lastMDUCycle + repeat_rate);
return -1;
@@ -173,7 +173,7 @@ MultDivUnit::getSlot(DynInstPtr inst)
rval);
if (rval != -1) {
lastMDUCycle = curTick;
lastMDUCycle = curTick();
lastOpType = inst->opClass();
lastInstName = inst->staticInst->getName();
}