From 9cce68ca7119f1dccfb67af5d62574c43f276986 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 18 Jan 2024 16:37:16 +0000 Subject: [PATCH 1/4] arch-arm: Replace isSecure boolean with SecurityState enum Change-Id: If01b8b2811b2c028e669ea3700174c7945b07a06 Signed-off-by: Giacomo Travaglini --- src/arch/arm/insts/misc.cc | 131 +++++++----- src/arch/arm/insts/misc64.cc | 386 +++++++++++++++++----------------- src/arch/arm/insts/misc64.hh | 36 ++-- src/arch/arm/mmu.cc | 68 +++--- src/arch/arm/mmu.hh | 12 +- src/arch/arm/pagetable.hh | 23 +- src/arch/arm/stage2_lookup.cc | 4 +- src/arch/arm/stage2_lookup.hh | 9 +- src/arch/arm/table_walker.cc | 54 +++-- src/arch/arm/table_walker.hh | 13 +- src/arch/arm/tlb.cc | 17 +- src/arch/arm/tlbi_op.cc | 14 +- src/arch/arm/tlbi_op.hh | 89 ++++---- src/arch/arm/types.hh | 23 ++ src/arch/arm/utility.cc | 9 +- src/arch/arm/utility.hh | 2 +- 16 files changed, 477 insertions(+), 413 deletions(-) diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 78d489ec12..7c34823923 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -411,12 +411,13 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; - TLBIALL tlbiOp(TranslationRegime::EL10, secure); + TLBIALL tlbiOp(TranslationRegime::EL10, ss); if (shareable) { tlbiOp.broadcast(tc); } else { @@ -429,8 +430,9 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; - TLBIALL tlbiOp(TranslationRegime::EL10, secure); + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; + TLBIALL tlbiOp(TranslationRegime::EL10, ss); tlbiOp.broadcast(tc); return; } @@ -440,12 +442,13 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; - ITLBIALL tlbiOp(TranslationRegime::EL10, secure); + ITLBIALL tlbiOp(TranslationRegime::EL10, ss); if (shareable) { tlbiOp.broadcast(tc); } else { @@ -459,12 +462,13 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; - DTLBIALL tlbiOp(TranslationRegime::EL10, secure); + DTLBIALL tlbiOp(TranslationRegime::EL10, ss); if (shareable) { tlbiOp.broadcast(tc); } else { @@ -478,13 +482,14 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; TLBIMVA tlbiOp(TranslationRegime::EL10, - secure, + ss, mbits(value, 31, 12), bits(value, 7, 0), false); @@ -502,13 +507,14 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; TLBIMVA tlbiOp(TranslationRegime::EL10, - secure, + ss, mbits(value, 31, 12), bits(value, 7, 0), true); @@ -525,9 +531,10 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; TLBIMVA tlbiOp(TranslationRegime::EL10, - secure, + ss, mbits(value, 31, 12), bits(value, 7, 0), false); @@ -540,9 +547,10 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; TLBIMVA tlbiOp(TranslationRegime::EL10, - secure, + ss, mbits(value, 31, 12), bits(value, 7, 0), true); @@ -556,13 +564,14 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; TLBIASID tlbiOp(TranslationRegime::EL10, - secure, + ss, bits(value, 7, 0)); if (shareable) { @@ -577,9 +586,10 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; TLBIASID tlbiOp(TranslationRegime::EL10, - secure, + ss, bits(value, 7, 0)); tlbiOp.broadcast(tc); @@ -591,11 +601,12 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; - TLBIMVAA tlbiOp(TranslationRegime::EL10, secure, + TLBIMVAA tlbiOp(TranslationRegime::EL10, ss, mbits(value, 31, 12), false); if (shareable) { @@ -611,12 +622,13 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; - TLBIMVAA tlbiOp(TranslationRegime::EL10, secure, + TLBIMVAA tlbiOp(TranslationRegime::EL10, ss, mbits(value, 31, 12), true); if (shareable) { @@ -631,8 +643,9 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; - TLBIMVAA tlbiOp(TranslationRegime::EL10, secure, + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; + TLBIMVAA tlbiOp(TranslationRegime::EL10, ss, mbits(value, 31, 12), false); tlbiOp.broadcast(tc); @@ -643,8 +656,9 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; - TLBIMVAA tlbiOp(TranslationRegime::EL10, secure, + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; + TLBIMVAA tlbiOp(TranslationRegime::EL10, ss, mbits(value, 31, 12), true); tlbiOp.broadcast(tc); @@ -655,8 +669,9 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; - TLBIMVAA tlbiOp(TranslationRegime::EL2, secure, + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; + TLBIMVAA tlbiOp(TranslationRegime::EL2, ss, mbits(value, 31, 12), false); tlbiOp(tc); @@ -667,8 +682,9 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; - TLBIMVAA tlbiOp(TranslationRegime::EL2, secure, + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; + TLBIMVAA tlbiOp(TranslationRegime::EL2, ss, mbits(value, 31, 12), true); tlbiOp(tc); @@ -679,8 +695,9 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; - TLBIMVAA tlbiOp(TranslationRegime::EL2, secure, + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; + TLBIMVAA tlbiOp(TranslationRegime::EL2, ss, mbits(value, 31, 12), false); tlbiOp.broadcast(tc); @@ -691,8 +708,9 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; - TLBIMVAA tlbiOp(TranslationRegime::EL2, secure, + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; + TLBIMVAA tlbiOp(TranslationRegime::EL2, ss, mbits(value, 31, 12), true); tlbiOp.broadcast(tc); @@ -703,9 +721,10 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; TLBIIPA tlbiOp(TranslationRegime::EL10, - secure, + ss, static_cast(bits(value, 35, 0)) << 12, false); @@ -718,9 +737,10 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; TLBIIPA tlbiOp(TranslationRegime::EL10, - secure, + ss, static_cast(bits(value, 35, 0)) << 12, true); @@ -733,9 +753,10 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; TLBIIPA tlbiOp(TranslationRegime::EL10, - secure, + ss, static_cast(bits(value, 35, 0)) << 12, false); @@ -748,9 +769,10 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const { SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; TLBIIPA tlbiOp(TranslationRegime::EL10, - secure, + ss, static_cast(bits(value, 35, 0)) << 12, true); @@ -763,12 +785,14 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; + ITLBIMVA tlbiOp(TranslationRegime::EL10, - secure, + ss, mbits(value, 31, 12), bits(value, 7, 0)); @@ -785,13 +809,14 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; DTLBIMVA tlbiOp(TranslationRegime::EL10, - secure, + ss, mbits(value, 31, 12), bits(value, 7, 0)); @@ -808,13 +833,14 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; ITLBIASID tlbiOp(TranslationRegime::EL10, - secure, + ss, bits(value, 7, 0)); if (shareable) { @@ -830,13 +856,14 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && !scr.ns; + auto ss = release->has(ArmExtension::SECURITY) && !scr.ns ? + SecurityState::Secure : SecurityState::NonSecure; // Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1 bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) && hcr.fb && !hcr.tge; DTLBIASID tlbiOp(TranslationRegime::EL10, - secure, + ss, bits(value, 7, 0)); if (shareable) { diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index b5b8ce7415..cc149dd676 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -247,10 +247,10 @@ RegNone::generateDisassembly( void TlbiOp64::tlbiAll(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, + SecurityState ss, TranslationRegime regime, bool shareable, TlbiAttr attrs) { - TLBIALLEL tlbi_op(regime, secure, attrs); + TLBIALLEL tlbi_op(regime, ss, attrs); if (shareable) { tlbi_op.broadcast(tc); } else { @@ -260,10 +260,10 @@ TlbiOp64::tlbiAll(ThreadContext *tc, RegVal value, void TlbiOp64::tlbiVmall(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, bool stage2, - TlbiAttr attrs) + SecurityState ss, TranslationRegime regime, bool shareable, + bool stage2, TlbiAttr attrs) { - TLBIVMALL tlbi_op(regime, secure, stage2, attrs); + TLBIVMALL tlbi_op(regime, ss, stage2, attrs); if (shareable) { tlbi_op.broadcast(tc); } else { @@ -273,8 +273,8 @@ TlbiOp64::tlbiVmall(ThreadContext *tc, RegVal value, void TlbiOp64::tlbiVa(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, bool last_level, - TlbiAttr attrs) + SecurityState ss, TranslationRegime regime, bool shareable, + bool last_level, TlbiAttr attrs) { if (MMU::hasUnprivRegime(regime)) { // The asid will only be used when e2h == 1 @@ -282,7 +282,7 @@ TlbiOp64::tlbiVa(ThreadContext *tc, RegVal value, auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); - TLBIMVA tlbi_op(regime, secure, static_cast(bits(value, 43, 0)) << 12, + TLBIMVA tlbi_op(regime, ss, static_cast(bits(value, 43, 0)) << 12, asid, last_level, attrs); if (shareable) { tlbi_op.broadcast(tc); @@ -290,7 +290,7 @@ TlbiOp64::tlbiVa(ThreadContext *tc, RegVal value, tlbi_op(tc); } } else { - TLBIMVAA tlbi_op(regime, secure, + TLBIMVAA tlbi_op(regime, ss, static_cast(bits(value, 43, 0)) << 12, last_level, attrs); if (shareable) { @@ -303,13 +303,12 @@ TlbiOp64::tlbiVa(ThreadContext *tc, RegVal value, void TlbiOp64::tlbiVaa(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, bool last_level, - TlbiAttr attrs) + SecurityState ss, TranslationRegime regime, bool shareable, + bool last_level, TlbiAttr attrs) { - TLBIMVAA tlbi_op(regime, secure, + TLBIMVAA tlbi_op(regime, ss, static_cast(bits(value, 43, 0)) << 12, last_level, attrs); - if (shareable) { tlbi_op.broadcast(tc); } else { @@ -319,14 +318,14 @@ TlbiOp64::tlbiVaa(ThreadContext *tc, RegVal value, void TlbiOp64::tlbiAsid(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, + SecurityState ss, TranslationRegime regime, bool shareable, TlbiAttr attrs) { bool asid_16bits = ArmSystem::haveLargeAsid64(tc); auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); - TLBIASID tlbi_op(regime, secure, asid, attrs); + TLBIASID tlbi_op(regime, ss, asid, attrs); if (shareable) { tlbi_op.broadcast(tc); } else { @@ -336,20 +335,17 @@ TlbiOp64::tlbiAsid(ThreadContext *tc, RegVal value, void TlbiOp64::tlbiIpaS2(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, bool last_level, - TlbiAttr attrs) + SecurityState ss, TranslationRegime regime, bool shareable, + bool last_level, TlbiAttr attrs) { if (EL2Enabled(tc)) { - auto isa = static_cast(tc->getIsaPtr()); - auto release = isa->getRelease(); - - SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && - !scr.ns && !bits(value, 63); + if (ss == SecurityState::Secure && bits(value, 63)) { + ss = SecurityState::NonSecure; + } const int top_bit = ArmSystem::physAddrRange(tc) == 52 ? 39 : 35; - TLBIIPA tlbi_op(TranslationRegime::EL10, secure, + TLBIIPA tlbi_op(TranslationRegime::EL10, ss, static_cast(bits(value, top_bit, 0)) << 12, last_level, attrs); @@ -363,10 +359,10 @@ TlbiOp64::tlbiIpaS2(ThreadContext *tc, RegVal value, void TlbiOp64::tlbiRvaa(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, bool last_level, - TlbiAttr attrs) + SecurityState ss, TranslationRegime regime, bool shareable, + bool last_level, TlbiAttr attrs) { - TLBIRMVAA tlbi_op(regime, secure, value, last_level, attrs); + TLBIRMVAA tlbi_op(regime, ss, value, last_level, attrs); if (shareable) { tlbi_op.broadcast(tc); } else { @@ -376,7 +372,7 @@ TlbiOp64::tlbiRvaa(ThreadContext *tc, RegVal value, void TlbiOp64::tlbiRva(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, bool last_level, + SecurityState ss, TranslationRegime regime, bool shareable, bool last_level, TlbiAttr attrs) { if (MMU::hasUnprivRegime(regime)) { @@ -385,30 +381,28 @@ TlbiOp64::tlbiRva(ThreadContext *tc, RegVal value, auto asid = asid_16bits ? bits(value, 63, 48) : bits(value, 55, 48); - TLBIRMVA tlbi_op(regime, secure, value, asid, last_level, attrs); + TLBIRMVA tlbi_op(regime, ss, value, asid, last_level, attrs); if (shareable) { tlbi_op.broadcast(tc); } else { tlbi_op(tc); } } else { - tlbiRvaa(tc, value, secure, regime, shareable, last_level, attrs); + tlbiRvaa(tc, value, ss, regime, shareable, last_level, attrs); } } void TlbiOp64::tlbiRipaS2(ThreadContext *tc, RegVal value, - bool secure, TranslationRegime regime, bool shareable, bool last_level, - TlbiAttr attrs) + SecurityState ss, TranslationRegime regime, bool shareable, + bool last_level, TlbiAttr attrs) { if (EL2Enabled(tc)) { - auto isa = static_cast(tc->getIsaPtr()); - auto release = isa->getRelease(); - SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); - bool secure = release->has(ArmExtension::SECURITY) && - !scr.ns && !bits(value, 63); + if (ss == SecurityState::Secure && bits(value, 63)) { + ss = SecurityState::NonSecure; + } - TLBIRIPA tlbi_op(TranslationRegime::EL10, secure, value, + TLBIRIPA tlbi_op(TranslationRegime::EL10, ss, value, last_level, attrs); if (shareable) { @@ -433,7 +427,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE3, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime false); // shareable } @@ -442,7 +436,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE3NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime false, // shareable TlbiAttr::ExcludeXS); // attrs @@ -452,7 +446,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE3IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true); // shareable } @@ -461,7 +455,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE3ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable TlbiAttr::ExcludeXS); // attrs @@ -471,7 +465,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE3OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true); // shareable } @@ -480,7 +474,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE3OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable TlbiAttr::ExcludeXS); // attrs @@ -494,7 +488,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false); // shareable } @@ -506,7 +500,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable TlbiAttr::ExcludeXS); // attrs @@ -519,7 +513,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true); // shareable } @@ -531,7 +525,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable TlbiAttr::ExcludeXS); // attrs @@ -544,7 +538,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true); // shareable } @@ -556,7 +550,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable TlbiAttr::ExcludeXS); // attrs @@ -566,7 +560,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE1, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false); // shareable } @@ -575,7 +569,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE1NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable TlbiAttr::ExcludeXS); // attrs @@ -585,7 +579,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE1IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true); // shareable } @@ -594,7 +588,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE1ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable TlbiAttr::ExcludeXS); // attrs @@ -604,7 +598,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE1OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true); // shareable } @@ -613,7 +607,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_ALLE1OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiAll(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable TlbiAttr::ExcludeXS); // attrs @@ -635,7 +629,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // stage2 @@ -654,7 +648,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // stage2 @@ -671,7 +665,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // stage2 @@ -685,7 +679,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // stage2 @@ -702,7 +696,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // stage2 @@ -716,7 +710,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // stage2 @@ -727,7 +721,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VMALLS12E1, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable true); // stage2 @@ -737,7 +731,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VMALLS12E1NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable true, // stage2 @@ -748,7 +742,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VMALLS12E1IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true); // stage2 @@ -758,7 +752,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VMALLS12E1ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true, // stage2 @@ -769,7 +763,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VMALLS12E1OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true); // stage2 @@ -779,7 +773,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VMALLS12E1OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVmall(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true, // stage2 @@ -791,7 +785,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE3, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime false, // shareable false); // last level only @@ -801,7 +795,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE3NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime false, // shareable false, // last level only @@ -813,7 +807,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE3IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable false); // last level only @@ -823,7 +817,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE3ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable false, // last level only @@ -834,7 +828,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE3OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable false); // last level only @@ -844,7 +838,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE3OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable false, // last level only @@ -856,7 +850,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VALE3, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime false, // shareable true); // last level only @@ -866,7 +860,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VALE3NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime false, // shareable true, // last level only @@ -878,7 +872,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VALE3IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable true); // last level only @@ -888,7 +882,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VALE3ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable true, // last level only @@ -900,7 +894,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VALE3OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable true); // last level only @@ -910,7 +904,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VALE3OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - true, // secure + SecurityState::Secure, // secure TranslationRegime::EL3, // regime true, // shareable true, // last level only @@ -924,7 +918,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable false); // last level only @@ -937,7 +931,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable false, // last level only @@ -948,7 +942,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE2IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure TranslationRegime::EL2, // regime true, // shareable false); // last level only @@ -958,7 +952,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE2ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure TranslationRegime::EL2, // regime true, // shareable false, // last level only @@ -970,7 +964,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE2OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc,EL2), // secure + securityStateAtEL(tc,EL2), // secure TranslationRegime::EL2, // regime true, // shareable false); // last level only @@ -980,7 +974,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_VAE2OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc,EL2), // secure + securityStateAtEL(tc,EL2), // secure TranslationRegime::EL2, // regime true, // shareable false, // last level only @@ -995,7 +989,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable true); // last level only @@ -1008,7 +1002,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable true, // last level only @@ -1022,7 +1016,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable true); // last level only @@ -1035,7 +1029,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable true, // last level only @@ -1049,7 +1043,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable true); // last level only @@ -1062,7 +1056,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable true, // last level only @@ -1084,7 +1078,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // last level only @@ -1103,7 +1097,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // last level only @@ -1120,7 +1114,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1134,7 +1128,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1151,7 +1145,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1165,7 +1159,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1182,7 +1176,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime false, // shareable true, // last level only @@ -1201,7 +1195,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable true, // last level only @@ -1218,7 +1212,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -1232,7 +1226,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -1249,7 +1243,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -1263,7 +1257,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -1285,7 +1279,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiAsid(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable attrs); // attrs @@ -1303,7 +1297,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiAsid(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable TlbiAttr::ExcludeXS); // attrs @@ -1319,7 +1313,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiAsid(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable attrs); // attrs @@ -1332,7 +1326,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiAsid(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable TlbiAttr::ExcludeXS); // attrs @@ -1348,7 +1342,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiAsid(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable attrs); // attrs @@ -1361,7 +1355,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiAsid(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable TlbiAttr::ExcludeXS); // attrs @@ -1382,7 +1376,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // last level only @@ -1401,7 +1395,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // last level @@ -1418,7 +1412,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1432,7 +1426,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level @@ -1449,7 +1443,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1463,7 +1457,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level @@ -1485,7 +1479,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable true, // last level only @@ -1504,7 +1498,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable true, // last level @@ -1521,7 +1515,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -1535,7 +1529,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level @@ -1552,7 +1546,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -1566,7 +1560,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiVaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level @@ -1577,7 +1571,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2E1, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable false); // last level @@ -1587,7 +1581,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2E1NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable false, // last level @@ -1598,7 +1592,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2E1IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false); // last level @@ -1608,7 +1602,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2E1ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false, // last level @@ -1620,7 +1614,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2E1OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false); // last level @@ -1630,7 +1624,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2E1OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false, // last level @@ -1641,7 +1635,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2LE1, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable true); // last level @@ -1651,7 +1645,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2LE1NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable true, // last level @@ -1663,7 +1657,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2LE1IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true); // last level @@ -1673,7 +1667,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2LE1ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true, // last level @@ -1685,7 +1679,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2LE1OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true); // last level @@ -1695,7 +1689,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_IPAS2LE1OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiIpaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true, // last level @@ -1718,7 +1712,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // last level only @@ -1737,7 +1731,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // last level only @@ -1754,7 +1748,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1768,7 +1762,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1785,7 +1779,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1799,7 +1793,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1821,7 +1815,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // last level only @@ -1840,7 +1834,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable false, // last level only @@ -1857,7 +1851,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1871,7 +1865,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1889,7 +1883,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1903,7 +1897,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable false, // last level only @@ -1925,7 +1919,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable true, // last level only @@ -1944,7 +1938,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable true, // last level only @@ -1961,7 +1955,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -1975,7 +1969,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -1992,7 +1986,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -2006,7 +2000,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -2028,7 +2022,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable true, // last level only @@ -2047,7 +2041,7 @@ std::unordered_map TlbiOp64::tlbiOps = { hcr.fb && !hcr.tge; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime shareable, // shareable true, // last level only @@ -2064,7 +2058,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -2078,7 +2072,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -2095,7 +2089,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TlbiAttr::ExcludeXS : TlbiAttr::None; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -2109,7 +2103,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL10; TlbiOp64::tlbiRvaa(tc, value, - isSecureAtEL(tc, translationEl(regime)), // secure + securityStateAtEL(tc, translationEl(regime)), // secure regime, // regime true, // shareable true, // last level only @@ -2120,7 +2114,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2E1, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable false); // last level only @@ -2130,7 +2124,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2E1NXS, [](ThreadContext *tc, RegVal value) { tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable false, // last level only @@ -2142,7 +2136,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2E1IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false); // last level only @@ -2152,7 +2146,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2E1ISNXS, [](ThreadContext *tc, RegVal value) { tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false, // last level only @@ -2163,7 +2157,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2E1OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false); // last level only @@ -2173,7 +2167,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2E1OSNXS, [](ThreadContext *tc, RegVal value) { tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false, // last level only @@ -2184,7 +2178,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2E1OS, [](ThreadContext *tc, RegVal value) { tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false); // last level only @@ -2194,7 +2188,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2E1OSNXS, [](ThreadContext *tc, RegVal value) { tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable false, // last level only @@ -2205,7 +2199,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2LE1, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable true); // last level only @@ -2215,7 +2209,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2LE1NXS, [](ThreadContext *tc, RegVal value) { tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime false, // shareable true, // last level only @@ -2226,7 +2220,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2LE1IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true); // last level only @@ -2236,7 +2230,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2LE1ISNXS, [](ThreadContext *tc, RegVal value) { tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true, // last level only @@ -2247,7 +2241,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2LE1OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true); // last level only @@ -2257,7 +2251,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RIPAS2LE1OSNXS, [](ThreadContext *tc, RegVal value) { tlbiRipaS2(tc, value, - isSecureAtEL(tc, EL1), // secure + securityStateAtEL(tc, EL1), // secure TranslationRegime::EL10, // regime true, // shareable true, // last level only @@ -2271,7 +2265,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable false); // last level only @@ -2284,7 +2278,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable false, // last level only @@ -2298,7 +2292,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable false); // last level only @@ -2311,7 +2305,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable false, // last level only @@ -2325,7 +2319,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable false); // last level only @@ -2338,7 +2332,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable false, // last level only @@ -2352,7 +2346,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable true); // last level only @@ -2365,7 +2359,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime false, // shareable true, // last level only @@ -2379,7 +2373,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable true); // last level only @@ -2392,7 +2386,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable true, // last level only @@ -2406,7 +2400,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable true); // last level only @@ -2419,7 +2413,7 @@ std::unordered_map TlbiOp64::tlbiOps = { TranslationRegime::EL20 : TranslationRegime::EL2; TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL2), // secure + securityStateAtEL(tc, EL2), // secure regime, // regime true, // shareable true, // last level only @@ -2430,7 +2424,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVAE3, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime false, // shareable false); // last level only @@ -2440,7 +2434,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVAE3NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime false, // shareable false, // last level only @@ -2451,7 +2445,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVAE3IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime true, // shareable false); // last level only @@ -2461,7 +2455,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVAE3ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime true, // shareable false, // last level only @@ -2472,7 +2466,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVAE3OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime true, // shareable false); // last level only @@ -2482,7 +2476,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVAE3OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime true, // shareable false, // last level only @@ -2493,7 +2487,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVALE3, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime false, // shareable true); // last level only @@ -2503,7 +2497,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVALE3NXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime false, // shareable true, // last level only @@ -2514,7 +2508,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVALE3IS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime true, // shareable true); // last level only @@ -2524,7 +2518,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVALE3ISNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime true, // shareable true, // last level only @@ -2535,7 +2529,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVALE3OS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime true, // shareable true); // last level only @@ -2545,7 +2539,7 @@ std::unordered_map TlbiOp64::tlbiOps = { { MISCREG_TLBI_RVALE3OSNXS, [](ThreadContext *tc, RegVal value) { TlbiOp64::tlbiRva(tc, value, - isSecureAtEL(tc, EL3), // secure + securityStateAtEL(tc, EL3), // secure TranslationRegime::EL3, // regime true, // shareable true, // last level only diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh index 7ce3b188c5..78c29e585e 100644 --- a/src/arch/arm/insts/misc64.hh +++ b/src/arch/arm/insts/misc64.hh @@ -292,40 +292,40 @@ class TlbiOp64 : public MiscRegRegImmOp64 static std::unordered_map tlbiOps; static void tlbiAll(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, TlbiAttr attrs=TlbiAttr::None); static void tlbiVmall(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - bool stage2=false, TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, bool stage2=false, TlbiAttr attrs=TlbiAttr::None); static void tlbiVa(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - bool last_level, TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None); static void tlbiVaa(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - bool last_level, TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None); static void tlbiAsid(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, TlbiAttr attrs=TlbiAttr::None); static void tlbiIpaS2(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - bool last_level, TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None); static void tlbiRvaa(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - bool last_level, TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None); static void tlbiRva(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - bool last_level, TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None); static void tlbiRipaS2(ThreadContext *tc, RegVal value, - bool secure, ArmISA::TranslationRegime regime, bool shareable, - bool last_level, TlbiAttr attrs=TlbiAttr::None); + ArmISA::SecurityState ss, ArmISA::TranslationRegime regime, + bool shareable, bool last_level, TlbiAttr attrs=TlbiAttr::None); static bool fnxsAttrs(ThreadContext *tc); diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc index 44c3bb3d97..3df8b9356c 100644 --- a/src/arch/arm/mmu.cc +++ b/src/arch/arm/mmu.cc @@ -179,7 +179,7 @@ MMU::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) lookup_data.asn = state.asid; lookup_data.ignoreAsn = false; lookup_data.vmid = state.vmid; - lookup_data.secure = state.isSecure; + lookup_data.ss = state.securityState; lookup_data.functional = true; lookup_data.targetRegime = state.currRegime; lookup_data.mode = BaseMMU::Read; @@ -459,7 +459,8 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode, (ap == 3 && state.sctlr.uwxn && is_priv); if (is_fetch && (abt || xn || (te->longDescFormat && te->pxn && is_priv) || - (state.isSecure && te->ns && state.scr.sif))) { + (state.securityState == SecurityState::Secure && + te->ns && state.scr.sif))) { stats.permsFaults++; DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n", @@ -615,7 +616,8 @@ MMU::s2PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode, uint8_t xn = te->xn; uint8_t pxn = te->pxn; - if (ArmSystem::haveEL(tc, EL3) && state.isSecure && + if (ArmSystem::haveEL(tc, EL3) && + state.securityState == SecurityState::Secure && te->ns && state.scr.sif) { xn = true; } @@ -705,7 +707,8 @@ MMU::s1PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode, // if wxn is set grant_exec = grant_exec && !(wxn && grant_write); - if (ArmSystem::haveEL(tc, EL3) && state.isSecure && te->ns) { + if (ArmSystem::haveEL(tc, EL3) && + state.securityState == SecurityState::Secure && te->ns) { grant_exec = grant_exec && !state.scr.sif; } @@ -811,7 +814,7 @@ MMU::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode, req->setPaddr(vaddr); // When the MMU is off the security attribute corresponds to the // security state of the processor - if (state.isSecure) + if (state.securityState == SecurityState::Secure) req->setFlags(Request::SECURE); else req->clearFlags(Request::SECURE); @@ -846,8 +849,9 @@ MMU::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode, } // Set memory attributes + bool in_secure_state = state.securityState == SecurityState::Secure; TlbEntry temp_te; - temp_te.ns = !state.isSecure; + temp_te.ns = !in_secure_state; bool dc = (HaveExt(tc, ArmExtension::FEAT_VHE) && state.hcr.e2h == 1 && state.hcr.tge == 1) ? 0: state.hcr.dc; bool i_cacheability = state.sctlr.i && !state.sctlr.m; @@ -916,7 +920,7 @@ MMU::translateMmuOn(ThreadContext* tc, const RequestPtr &req, Mode mode, Addr pa = te->pAddr(vaddr); req->setPaddr(pa); - if (state.isSecure && !te->ns) { + if (state.securityState == SecurityState::Secure && !te->ns) { req->setFlags(Request::SECURE); } else { req->clearFlags(Request::SECURE); @@ -969,7 +973,8 @@ MMU::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", - state.isPriv, flags & UserMode, state.isSecure, + state.isPriv, flags & UserMode, + state.securityState == SecurityState::Secure, tran_type & S1S2NsTran); DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " @@ -1214,8 +1219,9 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc, scr = tc->readMiscReg(MISCREG_SCR_EL3); // Dependencies: SCR/SCR_EL3, CPSR - isSecure = ArmISA::isSecure(tc) && - !(tran_type & HypMode) && !(tran_type & S1S2NsTran); + securityState = ArmISA::isSecure(tc) && + !(tran_type & HypMode) && !(tran_type & S1S2NsTran) ? + SecurityState::Secure : SecurityState::NonSecure; exceptionLevel = tranTypeEL(cpsr, scr, tran_type); currRegime = translationRegime(tc, exceptionLevel); @@ -1296,27 +1302,27 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc, } } else { // AArch32 sctlr = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc, - !isSecure)); + securityState == SecurityState::NonSecure)); ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc, - !isSecure)); + securityState == SecurityState::NonSecure)); isPriv = cpsr.mode != MODE_USER; if (longDescFormatInUse(tc)) { uint64_t ttbr_asid = tc->readMiscReg( - snsBankedIndex(ttbcr.a1 ? MISCREG_TTBR1 : - MISCREG_TTBR0, - tc, !isSecure)); + snsBankedIndex(ttbcr.a1 ? MISCREG_TTBR1 : MISCREG_TTBR0, + tc, securityState == SecurityState::NonSecure)); asid = bits(ttbr_asid, 55, 48); } else { // Short-descriptor translation table format in use CONTEXTIDR context_id = tc->readMiscReg(snsBankedIndex( - MISCREG_CONTEXTIDR, tc,!isSecure)); + MISCREG_CONTEXTIDR, tc, + securityState == SecurityState::NonSecure)); asid = context_id.asid; } prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, tc, - !isSecure)); + securityState == SecurityState::NonSecure)); nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, tc, - !isSecure)); + securityState == SecurityState::NonSecure)); dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc, - !isSecure)); + securityState == SecurityState::NonSecure)); if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) { vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); @@ -1379,15 +1385,15 @@ MMU::tranTypeEL(CPSR cpsr, SCR scr, ArmTranslationType type) Fault MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, - bool is_secure, ArmTranslationType tran_type, + SecurityState ss, ArmTranslationType tran_type, bool stage2) { return getTE(te, req, tc, mode, translation, timing, functional, - is_secure, tran_type, stage2 ? s2State : s1State); + ss, tran_type, stage2 ? s2State : s1State); } TlbEntry* -MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, bool secure, +MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, SecurityState ss, bool functional, bool ignore_asn, TranslationRegime regime, bool stage2, BaseMMU::Mode mode) { @@ -1399,7 +1405,7 @@ MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, bool secure, lookup_data.asn = asid; lookup_data.ignoreAsn = ignore_asn; lookup_data.vmid = vmid; - lookup_data.secure = secure; + lookup_data.ss = ss; lookup_data.functional = functional; lookup_data.targetRegime = regime; lookup_data.mode = mode; @@ -1410,7 +1416,7 @@ MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, bool secure, Fault MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, - bool is_secure, ArmTranslationType tran_type, + SecurityState ss, ArmTranslationType tran_type, CachedState& state) { // In a 2-stage system, the IPA->PA translation can be started via this @@ -1430,7 +1436,7 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, vaddr = vaddr_tainted; } - *te = lookup(vaddr, state.asid, state.vmid, is_secure, false, + *te = lookup(vaddr, state.asid, state.vmid, ss, false, false, regime, state.isStage2, mode); if (!isCompleteTranslation(*te)) { @@ -1452,7 +1458,7 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Fault fault; fault = getTableWalker(mode, state.isStage2)->walk( req, tc, state.asid, state.vmid, mode, - translation, timing, functional, is_secure, + translation, timing, functional, ss, tran_type, state.stage2DescReq, *te); // for timing mode, return and wait for table walk, @@ -1460,7 +1466,7 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, return fault; } - *te = lookup(vaddr, state.asid, state.vmid, is_secure, + *te = lookup(vaddr, state.asid, state.vmid, ss, true, false, regime, state.isStage2, mode); assert(*te); } @@ -1481,7 +1487,7 @@ MMU::getResultTe(TlbEntry **te, const RequestPtr &req, TlbEntry *s2_te = nullptr; // Get the stage 2 table entry fault = getTE(&s2_te, req, tc, mode, translation, timing, functional, - state.isSecure, state.curTranType, state); + state.securityState, state.curTranType, state); // Check permissions of stage 2 if (isCompleteTranslation(s2_te) && (fault == NoFault)) { if (state.aarch64) @@ -1499,7 +1505,7 @@ MMU::getResultTe(TlbEntry **te, const RequestPtr &req, // Get the stage 1 table entry fault = getTE(&s1_te, req, tc, mode, translation, timing, functional, - state.isSecure, state.curTranType, state); + state.securityState, state.curTranType, state); // only proceed if we have a valid table entry if (isCompleteTranslation(s1_te) && (fault == NoFault)) { // Check stage 1 permissions before checking stage 2 @@ -1509,8 +1515,8 @@ MMU::getResultTe(TlbEntry **te, const RequestPtr &req, fault = checkPermissions(s1_te, req, mode, state); if (state.stage2Req & (fault == NoFault)) { Stage2LookUp *s2_lookup = new Stage2LookUp(this, *s1_te, - req, translation, mode, timing, functional, state.isSecure, - state.curTranType); + req, translation, mode, timing, functional, + state.securityState, state.curTranType); fault = s2_lookup->getTe(tc, mergeTe); if (s2_lookup->isComplete()) { *te = mergeTe; diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh index 36d34faade..28b43e6a0c 100644 --- a/src/arch/arm/mmu.hh +++ b/src/arch/arm/mmu.hh @@ -149,7 +149,7 @@ class MMU : public BaseMMU sctlr = rhs.sctlr; scr = rhs.scr; isPriv = rhs.isPriv; - isSecure = rhs.isSecure; + securityState = rhs.securityState; ttbcr = rhs.ttbcr; asid = rhs.asid; vmid = rhs.vmid; @@ -184,7 +184,7 @@ class MMU : public BaseMMU SCTLR sctlr = 0; SCR scr = 0; bool isPriv = false; - bool isSecure = false; + SecurityState securityState = SecurityState::NonSecure; TTBCR ttbcr = 0; uint16_t asid = 0; vmid_t vmid = 0; @@ -397,7 +397,7 @@ class MMU : public BaseMMU * @param vpn virtual address * @param asn context id/address space id to use * @param vmid The virtual machine ID used for stage 2 translation - * @param secure if the lookup is secure + * @param ss security state of the PE * @param functional if the lookup should modify state * @param ignore_asn if on lookup asn should be ignored * @param target_regime selecting the translation regime @@ -405,19 +405,19 @@ class MMU : public BaseMMU * @return pointer to TLB entry if it exists */ TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid, - bool secure, bool functional, + SecurityState ss, bool functional, bool ignore_asn, TranslationRegime target_regime, bool stage2, BaseMMU::Mode mode); Fault getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, - bool is_secure, ArmTranslationType tran_type, + SecurityState ss, ArmTranslationType tran_type, bool stage2); Fault getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, - bool is_secure, ArmTranslationType tran_type, + SecurityState ss, ArmTranslationType tran_type, CachedState &state); Fault getResultTe(TlbEntry **te, const RequestPtr &req, diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh index 2d8c1566e0..ab17b3df0d 100644 --- a/src/arch/arm/pagetable.hh +++ b/src/arch/arm/pagetable.hh @@ -199,7 +199,7 @@ struct TlbEntry : public Serializable // The virtual machine ID used for stage 2 translation vmid_t vmid = 0; // if the lookup is secure - bool secure = false; + SecurityState ss = SecurityState::NonSecure; // if the lookup should modify state bool functional = false; // selecting the translation regime @@ -239,8 +239,8 @@ struct TlbEntry : public Serializable // True if the entry targets the non-secure physical address space bool ns; - // True if the entry was brought in from a non-secure page table - bool nstid; + // Security state of the translation regime + SecurityState ss; // Translation regime on insert, AARCH64 EL0&1, AARCH32 -> el=1 TranslationRegime regime; // This is used to distinguish between instruction and data entries @@ -271,7 +271,8 @@ struct TlbEntry : public Serializable innerAttrs(0), outerAttrs(0), ap(read_only ? 0x3 : 0), hap(0x3), domain(DomainType::Client), mtype(MemoryType::StronglyOrdered), longDescFormat(false), global(false), valid(true), - ns(true), nstid(true), regime(TranslationRegime::EL10), + ns(true), ss(SecurityState::NonSecure), + regime(TranslationRegime::EL10), type(TypeTLB::unified), partial(false), nonCacheable(uncacheable), shareable(false), outerShareable(false), xn(0), pxn(0), @@ -290,7 +291,8 @@ struct TlbEntry : public Serializable innerAttrs(0), outerAttrs(0), ap(0), hap(0x3), domain(DomainType::Client), mtype(MemoryType::StronglyOrdered), longDescFormat(false), global(false), valid(false), - ns(true), nstid(true), regime(TranslationRegime::EL10), + ns(true), ss(SecurityState::NonSecure), + regime(TranslationRegime::EL10), type(TypeTLB::unified), partial(false), nonCacheable(false), shareable(false), outerShareable(false), xn(0), pxn(0), xs(true) @@ -330,8 +332,7 @@ struct TlbEntry : public Serializable match(const Lookup &lookup) const { bool match = false; - if (valid && matchAddress(lookup) && - (lookup.secure == !nstid)) + if (valid && matchAddress(lookup) && lookup.ss == ss) { match = checkRegime(lookup.targetRegime); @@ -410,8 +411,8 @@ struct TlbEntry : public Serializable print() const { return csprintf("%#x, asn %d vmn %d ppn %#x size: %#x ap:%d " - "ns:%d nstid:%d g:%d xs: %d regime:%s", vpn << N, asid, vmid, - pfn << N, size, ap, ns, nstid, global, + "ns:%d ss:%s g:%d xs: %d regime:%s", vpn << N, asid, vmid, + pfn << N, size, ap, ns, ss, global, xs, regimeToStr(regime)); } @@ -428,7 +429,7 @@ struct TlbEntry : public Serializable SERIALIZE_SCALAR(global); SERIALIZE_SCALAR(valid); SERIALIZE_SCALAR(ns); - SERIALIZE_SCALAR(nstid); + SERIALIZE_ENUM(ss); SERIALIZE_ENUM(type); SERIALIZE_SCALAR(nonCacheable); SERIALIZE_ENUM(lookupLevel); @@ -458,7 +459,7 @@ struct TlbEntry : public Serializable UNSERIALIZE_SCALAR(global); UNSERIALIZE_SCALAR(valid); UNSERIALIZE_SCALAR(ns); - UNSERIALIZE_SCALAR(nstid); + UNSERIALIZE_ENUM(ss); UNSERIALIZE_ENUM(type); UNSERIALIZE_SCALAR(nonCacheable); UNSERIALIZE_ENUM(lookupLevel); diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc index 35239ac4e0..febfd60fee 100644 --- a/src/arch/arm/stage2_lookup.cc +++ b/src/arch/arm/stage2_lookup.cc @@ -57,7 +57,7 @@ Fault Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe) { fault = mmu->getTE(&stage2Te, req, tc, mode, this, timing, - functional, secure, tranType, true); + functional, ss, tranType, true); // Call finish if we're done already if ((fault != NoFault) || (stage2Te != NULL)) { @@ -193,7 +193,7 @@ Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req, if ((fault == NoFault) && (stage2Te == NULL)) { // OLD_LOOK: stage2Tlb fault = mmu->getTE(&stage2Te, req, tc, mode, this, - timing, functional, secure, tranType, true); + timing, functional, ss, tranType, true); } // Now we have the stage 2 table entry we need to merge it with the stage diff --git a/src/arch/arm/stage2_lookup.hh b/src/arch/arm/stage2_lookup.hh index b9b0a9b8d8..2192e244be 100644 --- a/src/arch/arm/stage2_lookup.hh +++ b/src/arch/arm/stage2_lookup.hh @@ -72,16 +72,17 @@ class Stage2LookUp : public BaseMMU::Translation Fault fault; bool complete; bool selfDelete; - bool secure; + SecurityState ss; public: Stage2LookUp(MMU *_mmu, TlbEntry s1_te, const RequestPtr &_req, MMU::Translation *_transState, BaseMMU::Mode _mode, bool _timing, - bool _functional, bool _secure, MMU::ArmTranslationType _tranType) : - mmu(_mmu), stage1Te(s1_te), s1Req(_req), + bool _functional, SecurityState _ss, + MMU::ArmTranslationType _tranType) + : mmu(_mmu), stage1Te(s1_te), s1Req(_req), transState(_transState), mode(_mode), timing(_timing), functional(_functional), tranType(_tranType), stage2Te(nullptr), - fault(NoFault), complete(false), selfDelete(false), secure(_secure) + fault(NoFault), complete(false), selfDelete(false), ss(_ss) { req = std::make_shared(); req->setVirt(s1_te.pAddr(s1Req->getVaddr()), s1Req->getSize(), diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index f2b9f03a4b..1ce2f65800 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -131,7 +131,7 @@ TableWalker::WalkerState::WalkerState() : vaddr(0), vaddr_tainted(0), sctlr(0), scr(0), cpsr(0), tcr(0), htcr(0), hcr(0), vtcr(0), - isWrite(false), isFetch(false), isSecure(false), + isWrite(false), isFetch(false), ss(SecurityState::NonSecure), isUncacheable(false), longDescData(std::nullopt), hpd(false), sh(0), irgn(0), orgn(0), stage2Req(false), stage2Tran(nullptr), timing(false), functional(false), @@ -295,7 +295,7 @@ Fault TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, vmid_t _vmid, MMU::Mode _mode, MMU::Translation *_trans, bool _timing, bool _functional, - bool secure, MMU::ArmTranslationType tranType, + SecurityState ss, MMU::ArmTranslationType tranType, bool _stage2Req, const TlbEntry *walk_entry) { assert(!(_functional && _timing)); @@ -364,8 +364,8 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, currState->functional = _functional; currState->mode = _mode; currState->tranType = tranType; - currState->isSecure = secure; - currState->secureLookup = secure; + currState->ss = ss; + currState->secureLookup = currState->ss == SecurityState::Secure; currState->physAddrRange = _physAddrRange; /** @todo These should be cached or grabbed from cached copies in @@ -411,9 +411,11 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, } } else { currState->sctlr = currState->tc->readMiscReg(snsBankedIndex( - MISCREG_SCTLR, currState->tc, !currState->isSecure)); + MISCREG_SCTLR, currState->tc, + currState->ss == SecurityState::NonSecure)); currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex( - MISCREG_TTBCR, currState->tc, !currState->isSecure)); + MISCREG_TTBCR, currState->tc, + currState->ss == SecurityState::NonSecure)); currState->htcr = currState->tc->readMiscReg(MISCREG_HTCR); currState->hcr = currState->tc->readMiscReg(MISCREG_HCR); currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR); @@ -504,7 +506,7 @@ TableWalker::processWalkWrapper() // Check if a previous walk filled this request already // @TODO Should this always be the TLB or should we look in the stage2 TLB? TlbEntry* te = mmu->lookup(currState->vaddr, currState->asid, - currState->vmid, currState->isSecure, true, false, + currState->vmid, currState->ss, true, false, currState->regime, isStage2, currState->mode); // Check if we still need to have a walk for this request. If the requesting @@ -585,7 +587,7 @@ TableWalker::processWalkWrapper() if (pendingQueue.size()) { currState = pendingQueue.front(); te = mmu->lookup(currState->vaddr, currState->asid, - currState->vmid, currState->isSecure, true, + currState->vmid, currState->ss, true, false, currState->regime, isStage2, currState->mode); } else { // Terminate the loop, nothing more to do @@ -607,7 +609,8 @@ TableWalker::processWalk() // For short descriptors, translation configs are held in // TTBR1. RegVal ttbr1 = currState->tc->readMiscReg(snsBankedIndex( - MISCREG_TTBR1, currState->tc, !currState->isSecure)); + MISCREG_TTBR1, currState->tc, + currState->ss == SecurityState::NonSecure)); const auto irgn0_mask = 0x1; const auto irgn1_mask = 0x40; @@ -644,7 +647,8 @@ TableWalker::processWalk() ArmFault::VmsaTran); } ttbr = currState->tc->readMiscReg(snsBankedIndex( - MISCREG_TTBR0, currState->tc, !currState->isSecure)); + MISCREG_TTBR0, currState->tc, + currState->ss == SecurityState::NonSecure)); } else { DPRINTF(TLB, " - Selecting TTBR1\n"); // Check if table walk is allowed when Security Extensions are enabled @@ -670,7 +674,7 @@ TableWalker::processWalk() Addr l1desc_addr = mbits(ttbr, 31, 14 - currState->ttbcr.n) | (bits(currState->vaddr, 31 - currState->ttbcr.n, 20) << 2); DPRINTF(TLB, " - Descriptor at address %#x (%s)\n", l1desc_addr, - currState->isSecure ? "s" : "ns"); + currState->ss == SecurityState::Secure ? "s" : "ns"); Request::Flags flag = Request::PT_WALK; if (uncacheableWalk()) { @@ -762,7 +766,8 @@ TableWalker::processWalkLPAE() ArmFault::LpaeTran); } ttbr = currState->tc->readMiscReg(snsBankedIndex( - MISCREG_TTBR0, currState->tc, !currState->isSecure)); + MISCREG_TTBR0, currState->tc, + currState->ss == SecurityState::NonSecure)); tsz = currState->ttbcr.t0sz; currState->isUncacheable = currState->ttbcr.irgn0 == 0; if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GiB @@ -787,7 +792,8 @@ TableWalker::processWalkLPAE() ArmFault::LpaeTran); } ttbr = currState->tc->readMiscReg(snsBankedIndex( - MISCREG_TTBR1, currState->tc, !currState->isSecure)); + MISCREG_TTBR1, currState->tc, + currState->ss == SecurityState::NonSecure)); tsz = currState->ttbcr.t1sz; currState->isUncacheable = currState->ttbcr.irgn1 == 0; // Lower limit >= 3 GiB @@ -818,14 +824,16 @@ TableWalker::processWalkLPAE() desc_addr = mbits(ttbr, 39, n) | (bits(currState->vaddr, n + 26, 30) << 3); DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", - desc_addr, currState->isSecure ? "s" : "ns"); + desc_addr, currState->ss == SecurityState::Secure ? + "s" : "ns"); } else { // Skip first-level lookup n = (tsz >= 2 ? 14 - tsz : 12); desc_addr = mbits(ttbr, 39, n) | (bits(currState->vaddr, n + 17, 21) << 3); DPRINTF(TLB, " - Descriptor at address %#x (%s) (long-desc.)\n", - desc_addr, currState->isSecure ? "s" : "ns"); + desc_addr, currState->ss == SecurityState::Secure ? + "s" : "ns"); } if (uncacheableWalk()) { @@ -1227,9 +1235,9 @@ TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, } else { assert(tc); PRRR prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, - currState->tc, !currState->isSecure)); + currState->tc, currState->ss == SecurityState::NonSecure)); NMRR nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, - currState->tc, !currState->isSecure)); + currState->tc, currState->ss == SecurityState::NonSecure)); DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr); uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0; switch(bits(texcb, 2,0)) { @@ -1391,7 +1399,7 @@ TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, // value of SCTLR.TRE MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; int reg_as_int = snsBankedIndex(reg, currState->tc, - !currState->isSecure); + currState->ss == SecurityState::NonSecure); uint32_t mair = currState->tc->readMiscReg(reg_as_int); attr = (mair >> (8 * (attrIndx % 4))) & 0xff; uint8_t attr_7_4 = bits(attr, 7, 4); @@ -1674,7 +1682,8 @@ TableWalker::doL1Descriptor() l2desc_addr = currState->l1Desc.l2Addr() | (bits(currState->vaddr, 19, 12) << 2); DPRINTF(TLB, "L1 descriptor points to page table at: %#x (%s)\n", - l2desc_addr, currState->isSecure ? "s" : "ns"); + l2desc_addr, currState->ss == SecurityState::Secure ? + "s" : "ns"); Request::Flags flag = Request::PT_WALK; @@ -2234,7 +2243,7 @@ TableWalker::insertPartialTableEntry(LongDescriptor &descriptor) te.domain = descriptor.domain(); te.lookupLevel = descriptor.lookupLevel; te.ns = !descriptor.secure(have_security, currState); - te.nstid = !currState->isSecure; + te.ss = currState->ss; te.type = TypeTLB::unified; te.regime = currState->regime; @@ -2280,7 +2289,7 @@ TableWalker::insertTableEntry(DescriptorBase &descriptor, bool long_descriptor) te.domain = descriptor.domain(); te.lookupLevel = descriptor.lookupLevel; te.ns = !descriptor.secure(have_security, currState); - te.nstid = !currState->isSecure; + te.ss = currState->ss; te.xn = descriptor.xn(); te.type = currState->mode == BaseMMU::Execute ? TypeTLB::instruction : TypeTLB::data; @@ -2379,7 +2388,8 @@ TableWalker::testWalk(const RequestPtr &walk_req, TlbEntry::DomainType domain, if (!test) { return NoFault; } else { - return test->walkCheck(walk_req, currState->vaddr, currState->isSecure, + return test->walkCheck(walk_req, currState->vaddr, + currState->ss == SecurityState::Secure, currState->el != EL0, currState->mode, domain, lookup_level); } diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index f8a8ec1b5d..5143913f4f 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -662,8 +662,9 @@ class TableWalker : public ClockedObject global(WalkerState *currState) const override { assert(currState && (type() == Block || type() == Page)); - if (!currState->aarch64 && (currState->isSecure && - !currState->secureLookup)) { + const bool secure_state = currState->ss == SecurityState::Secure; + if (!currState->aarch64 && secure_state && + !currState->secureLookup) { return false; // ARM ARM issue C B3.6.3 } else if (currState->aarch64) { if (!MMU::hasUnprivRegime(currState->regime)) { @@ -671,7 +672,7 @@ class TableWalker : public ClockedObject // in AArch64 for regimes without an unpriviledged // component return true; - } else if (currState->isSecure && !currState->secureLookup) { + } else if (secure_state && !currState->secureLookup) { return false; } } @@ -896,8 +897,8 @@ class TableWalker : public ClockedObject /** If the access is a fetch (for execution, and no-exec) must be checked?*/ bool isFetch; - /** If the access comes from the secure state. */ - bool isSecure; + /** Security State of the access */ + SecurityState ss; /** Whether lookups should be treated as using the secure state. * This is usually the same as isSecure, but can be set to false by the * long descriptor table attributes. */ @@ -1139,7 +1140,7 @@ class TableWalker : public ClockedObject Fault walk(const RequestPtr &req, ThreadContext *tc, uint16_t asid, vmid_t _vmid, BaseMMU::Mode mode, BaseMMU::Translation *_trans, - bool timing, bool functional, bool secure, + bool timing, bool functional, SecurityState ss, MMU::ArmTranslationType tran_type, bool stage2, const TlbEntry *walk_entry); diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 900b7d328d..a8216204f8 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -160,15 +160,16 @@ TLB::lookup(const Lookup &lookup_data) TlbEntry *retval = match(lookup_data); - DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x secure %d " - "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " + DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x ss %s " + "ppn %#x size: %#x pa: %#x ap:%d ns:%d ss:%s g:%d asid: %d " "xs: %d regime: %s\n", lookup_data.va, lookup_data.asn, retval ? "hit" : "miss", - lookup_data.vmid, lookup_data.secure, + lookup_data.vmid, lookup_data.ss, retval ? retval->pfn : 0, retval ? retval->size : 0, retval ? retval->pAddr(lookup_data.va) : 0, retval ? retval->ap : 0, - retval ? retval->ns : 0, retval ? retval->nstid : 0, + retval ? retval->ns : 0, + retval ? retval->ss : SecurityState::NonSecure, retval ? retval->global : 0, retval ? retval->asid : 0, retval ? retval->xs : 0, retval ? regimeToStr(retval->regime) : "None"); @@ -243,19 +244,19 @@ TLB::insert(TlbEntry &entry) { DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" - " ap:%#x domain:%#x ns:%d nstid:%d, xs:%d regime: %s\n", entry.pfn, + " ap:%#x domain:%#x ns:%d ss:%s xs:%d regime: %s\n", entry.pfn, entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, entry.global, entry.valid, entry.nonCacheable, entry.xn, entry.ap, static_cast(entry.domain), entry.ns, - entry.nstid, entry.xs, regimeToStr(entry.regime)); + entry.ss, entry.xs, regimeToStr(entry.regime)); if (table[size - 1].valid) DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x " - "size: %#x ap:%d ns:%d nstid:%d g:%d xs:%d regime: %s\n", + "size: %#x ap:%d ns:%d ss:%s g:%d xs:%d regime: %s\n", table[size-1].vpn << table[size-1].N, table[size-1].asid, table[size-1].vmid, table[size-1].pfn << table[size-1].N, table[size-1].size, table[size-1].ap, table[size-1].ns, - table[size-1].nstid, table[size-1].global, + table[size-1].ss, table[size-1].global, table[size-1].xs, regimeToStr(table[size-1].regime)); // inserting to MRU position and evicting the LRU one diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc index 36d6459044..fdb2a160dc 100644 --- a/src/arch/arm/tlbi_op.cc +++ b/src/arch/arm/tlbi_op.cc @@ -69,7 +69,7 @@ TLBIALL::operator()(ThreadContext* tc) bool TLBIALL::matchEntry(TlbEntry* te, vmid_t vmid) const { - return te->valid && secureLookup == !te->nstid && + return te->valid && ss == te->ss && (te->vmid == vmid || el2Enabled) && te->checkRegime(targetRegime); } @@ -115,7 +115,7 @@ TLBIALLEL::operator()(ThreadContext* tc) bool TLBIALLEL::matchEntry(TlbEntry* te, vmid_t vmid) const { - return te->valid && secureLookup == !te->nstid && + return te->valid && ss == te->ss && te->checkRegime(targetRegime); } @@ -136,7 +136,7 @@ TLBIVMALL::operator()(ThreadContext* tc) bool TLBIVMALL::matchEntry(TlbEntry* te, vmid_t vmid) const { - return te->valid && secureLookup == !te->nstid && + return te->valid && ss == te->ss && te->checkRegime(targetRegime) && (te->vmid == vmid || !el2Enabled || !useVMID(targetRegime)); } @@ -157,7 +157,7 @@ bool TLBIASID::matchEntry(TlbEntry* te, vmid_t vmid) const { return te->valid && te->asid == asid && - secureLookup == !te->nstid && + ss == te->ss && te->checkRegime(targetRegime) && (te->vmid == vmid || !el2Enabled || !useVMID(targetRegime)); } @@ -202,7 +202,7 @@ TLBIALLN::operator()(ThreadContext* tc) bool TLBIALLN::matchEntry(TlbEntry* te, vmid_t vmid) const { - return te->valid && te->nstid && + return te->valid && te->ss == SecurityState::NonSecure && te->checkRegime(targetRegime); } @@ -213,7 +213,7 @@ TLBIMVAA::lookupGen(vmid_t vmid) const lookup_data.va = sext<56>(addr); lookup_data.ignoreAsn = true; lookup_data.vmid = vmid; - lookup_data.secure = secureLookup; + lookup_data.ss = ss; lookup_data.functional = true; lookup_data.targetRegime = targetRegime; lookup_data.mode = BaseMMU::Read; @@ -247,7 +247,7 @@ TLBIMVA::lookupGen(vmid_t vmid) const lookup_data.asn = asid; lookup_data.ignoreAsn = false; lookup_data.vmid = vmid; - lookup_data.secure = secureLookup; + lookup_data.ss = ss; lookup_data.functional = true; lookup_data.targetRegime = targetRegime; lookup_data.mode = BaseMMU::Read; diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh index f505dc7686..36bd6c47f5 100644 --- a/src/arch/arm/tlbi_op.hh +++ b/src/arch/arm/tlbi_op.hh @@ -63,8 +63,8 @@ class TLBIOp ExcludeXS }; - TLBIOp(TranslationRegime _target_regime, bool _secure, Attr _attr) - : secureLookup(_secure), targetRegime(_target_regime), attr(_attr) + TLBIOp(TranslationRegime _target_regime, SecurityState _ss, Attr _attr) + : ss(_ss), targetRegime(_target_regime), attr(_attr) {} virtual ~TLBIOp() {} @@ -108,7 +108,7 @@ class TLBIOp return false; } - bool secureLookup; + SecurityState ss; TranslationRegime targetRegime; Attr attr; }; @@ -117,9 +117,9 @@ class TLBIOp class TLBIALL : public TLBIOp { public: - TLBIALL(TranslationRegime _target_regime, bool _secure, + TLBIALL(TranslationRegime _target_regime, SecurityState _ss, Attr _attr=Attr::None) - : TLBIOp(_target_regime, _secure, _attr), el2Enabled(false), + : TLBIOp(_target_regime, _ss, _attr), el2Enabled(false), currentEL(EL0) {} @@ -138,7 +138,7 @@ class TLBIALL : public TLBIOp TLBIALL makeStage2() const { - return TLBIALL(targetRegime, secureLookup, attr); + return TLBIALL(targetRegime, ss, attr); } bool el2Enabled; @@ -149,8 +149,8 @@ class TLBIALL : public TLBIOp class ITLBIALL : public TLBIALL { public: - ITLBIALL(TranslationRegime _target_regime, bool _secure) - : TLBIALL(_target_regime, _secure) + ITLBIALL(TranslationRegime _target_regime, SecurityState _ss) + : TLBIALL(_target_regime, _ss) {} void operator()(ThreadContext* tc) override; @@ -162,8 +162,8 @@ class ITLBIALL : public TLBIALL class DTLBIALL : public TLBIALL { public: - DTLBIALL(TranslationRegime _target_regime, bool _secure) - : TLBIALL(_target_regime, _secure) + DTLBIALL(TranslationRegime _target_regime, SecurityState _ss) + : TLBIALL(_target_regime, _ss) {} void operator()(ThreadContext* tc) override; @@ -175,8 +175,8 @@ class DTLBIALL : public TLBIALL class TLBIALLEL : public TLBIOp { public: - TLBIALLEL(TranslationRegime _target_regime, bool _secure, Attr _attr) - : TLBIOp(_target_regime, _secure, _attr) + TLBIALLEL(TranslationRegime _target_regime, SecurityState _ss, Attr _attr) + : TLBIOp(_target_regime, _ss, _attr) {} void operator()(ThreadContext* tc) override; @@ -194,7 +194,7 @@ class TLBIALLEL : public TLBIOp TLBIALLEL makeStage2() const { - return TLBIALLEL(targetRegime, secureLookup, attr); + return TLBIALLEL(targetRegime, ss, attr); } }; @@ -203,9 +203,9 @@ class TLBIALLEL : public TLBIOp class TLBIVMALL : public TLBIOp { public: - TLBIVMALL(TranslationRegime _target_regime, bool _secure, - bool _stage2, Attr _attr) - : TLBIOp(_target_regime, _secure, _attr), el2Enabled(false), + TLBIVMALL(TranslationRegime _target_regime, + SecurityState _ss, bool _stage2, Attr _attr) + : TLBIOp(_target_regime, _ss, _attr), el2Enabled(false), stage2(_stage2) {} @@ -222,7 +222,7 @@ class TLBIVMALL : public TLBIOp TLBIVMALL makeStage2() const { - return TLBIVMALL(targetRegime, secureLookup, false, attr); + return TLBIVMALL(targetRegime, ss, false, attr); } bool el2Enabled; @@ -233,9 +233,9 @@ class TLBIVMALL : public TLBIOp class TLBIASID : public TLBIOp { public: - TLBIASID(TranslationRegime _target_regime, bool _secure, + TLBIASID(TranslationRegime _target_regime, SecurityState _ss, uint16_t _asid, Attr _attr=Attr::None) - : TLBIOp(_target_regime, _secure, _attr), asid(_asid), + : TLBIOp(_target_regime, _ss, _attr), asid(_asid), el2Enabled(false) {} @@ -251,8 +251,9 @@ class TLBIASID : public TLBIOp class ITLBIASID : public TLBIASID { public: - ITLBIASID(TranslationRegime _target_regime, bool _secure, uint16_t _asid) - : TLBIASID(_target_regime, _secure, _asid) + ITLBIASID(TranslationRegime _target_regime, + SecurityState _ss, uint16_t _asid) + : TLBIASID(_target_regime, _ss, _asid) {} void operator()(ThreadContext* tc) override; @@ -264,8 +265,9 @@ class ITLBIASID : public TLBIASID class DTLBIASID : public TLBIASID { public: - DTLBIASID(TranslationRegime _target_regime, bool _secure, uint16_t _asid) - : TLBIASID(_target_regime, _secure, _asid) + DTLBIASID(TranslationRegime _target_regime, + SecurityState _ss, uint16_t _asid) + : TLBIASID(_target_regime, _ss, _asid) {} void operator()(ThreadContext* tc) override; @@ -278,7 +280,7 @@ class TLBIALLN : public TLBIOp { public: TLBIALLN(TranslationRegime _target_regime) - : TLBIOp(_target_regime, false, Attr::None) + : TLBIOp(_target_regime, SecurityState::NonSecure, Attr::None) {} void operator()(ThreadContext* tc) override; @@ -304,9 +306,9 @@ class TLBIMVAA : public TLBIOp protected: TlbEntry::Lookup lookupGen(vmid_t vmid) const; public: - TLBIMVAA(TranslationRegime _target_regime, bool _secure, + TLBIMVAA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, bool last_level, Attr _attr=Attr::None) - : TLBIOp(_target_regime, _secure, _attr), addr(_addr), + : TLBIOp(_target_regime, _ss, _attr), addr(_addr), lastLevel(last_level) {} @@ -325,10 +327,10 @@ class TLBIMVA : public TLBIOp TlbEntry::Lookup lookupGen(vmid_t vmid) const; public: - TLBIMVA(TranslationRegime _target_regime, bool _secure, + TLBIMVA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, uint16_t _asid, bool last_level, Attr _attr=Attr::None) - : TLBIOp(_target_regime, _secure, _attr), addr(_addr), asid(_asid), + : TLBIOp(_target_regime, _ss, _attr), addr(_addr), asid(_asid), lastLevel(last_level) {} @@ -345,9 +347,9 @@ class TLBIMVA : public TLBIOp class ITLBIMVA : public TLBIMVA { public: - ITLBIMVA(TranslationRegime _target_regime, bool _secure, + ITLBIMVA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, uint16_t _asid) - : TLBIMVA(_target_regime, _secure, _addr, _asid, false) + : TLBIMVA(_target_regime, _ss, _addr, _asid, false) {} void operator()(ThreadContext* tc) override; @@ -359,9 +361,9 @@ class ITLBIMVA : public TLBIMVA class DTLBIMVA : public TLBIMVA { public: - DTLBIMVA(TranslationRegime _target_regime, bool _secure, + DTLBIMVA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, uint16_t _asid) - : TLBIMVA(_target_regime, _secure, _addr, _asid, false) + : TLBIMVA(_target_regime, _ss, _addr, _asid, false) {} void operator()(ThreadContext* tc) override; @@ -428,10 +430,9 @@ class TLBIRange class TLBIIPA : public TLBIOp { public: - TLBIIPA(TranslationRegime _target_regime, bool _secure, Addr _addr, + TLBIIPA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, bool last_level, Attr _attr=Attr::None) - : TLBIOp(_target_regime, _secure, _attr), - addr(_addr), lastLevel(last_level) + : TLBIOp(_target_regime, _ss, _attr), addr(_addr), lastLevel(last_level) {} void operator()(ThreadContext* tc) override; @@ -452,7 +453,7 @@ class TLBIIPA : public TLBIOp virtual TLBIMVAA makeStage2() const { - return TLBIMVAA(targetRegime, secureLookup, addr, lastLevel, attr); + return TLBIMVAA(targetRegime, ss, addr, lastLevel, attr); } Addr addr; @@ -463,11 +464,10 @@ class TLBIIPA : public TLBIOp class TLBIRMVA : public TLBIRange, public TLBIMVA { public: - TLBIRMVA(TranslationRegime _target_regime, bool _secure, + TLBIRMVA(TranslationRegime _target_regime, SecurityState _ss, RegVal val, uint16_t _asid, bool last_level, Attr _attr) : TLBIRange(val), - TLBIMVA(_target_regime, _secure, startAddress(), - _asid, last_level, _attr) + TLBIMVA(_target_regime, _ss, startAddress(), _asid, last_level, _attr) {} bool matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override; @@ -477,10 +477,10 @@ class TLBIRMVA : public TLBIRange, public TLBIMVA class TLBIRMVAA : public TLBIRange, public TLBIMVAA { public: - TLBIRMVAA(TranslationRegime _target_regime, bool _secure, + TLBIRMVAA(TranslationRegime _target_regime, SecurityState _ss, RegVal val, bool last_level, Attr _attr) : TLBIRange(val), - TLBIMVAA(_target_regime, _secure, startAddress(), last_level, _attr) + TLBIMVAA(_target_regime, _ss, startAddress(), last_level, _attr) {} bool matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override; @@ -490,17 +490,16 @@ class TLBIRMVAA : public TLBIRange, public TLBIMVAA class TLBIRIPA : public TLBIRange, public TLBIIPA { public: - TLBIRIPA(TranslationRegime _target_regime, bool _secure, + TLBIRIPA(TranslationRegime _target_regime, SecurityState _ss, RegVal val, bool last_level, Attr _attr) : TLBIRange(val), - TLBIIPA(_target_regime, _secure, startAddress(), last_level, _attr) + TLBIIPA(_target_regime, _ss, startAddress(), last_level, _attr) {} virtual TLBIMVAA makeStage2() const { - return TLBIRMVAA(targetRegime, secureLookup, rangeData, - lastLevel, attr); + return TLBIRMVAA(targetRegime, ss, rangeData, lastLevel, attr); } }; diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 8d12356ec5..86c632c498 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -268,6 +268,13 @@ namespace ArmISA RND_NEAREST }; + /** Security State */ + enum class SecurityState + { + NonSecure, + Secure + }; + enum ExceptionLevel { EL0 = 0, @@ -487,6 +494,22 @@ namespace ArmISA } } + static inline std::ostream& + operator<<(std::ostream& os, SecurityState ss) + { + switch (ss) { + case SecurityState::NonSecure: + os << "NonSecure"; + break; + case SecurityState::Secure: + os << "Secure"; + break; + default: + panic("Invalid SecurityState\n"); + } + return os; + } + constexpr unsigned MaxSveVecLenInBits = 2048; static_assert(MaxSveVecLenInBits >= 128 && MaxSveVecLenInBits <= 2048 && diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 2e1ad146d6..73d878a2b9 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -89,13 +89,14 @@ isSecureBelowEL3(ThreadContext *tc) static_cast(tc->readMiscRegNoEffect(MISCREG_SCR_EL3)).ns == 0; } -bool -isSecureAtEL(ThreadContext *tc, ExceptionLevel el) +SecurityState +securityStateAtEL(ThreadContext *tc, ExceptionLevel el) { if (ArmSystem::haveEL(tc, EL3) && el == EL3) - return true; + return SecurityState::Secure; else - return isSecureBelowEL3(tc); + return isSecureBelowEL3(tc) ? SecurityState::Secure : + SecurityState::NonSecure; } ExceptionLevel diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 7e10f19ab3..f4fde661aa 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -217,7 +217,7 @@ int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr, bool isSecureBelowEL3(ThreadContext *tc); -bool isSecureAtEL(ThreadContext *tc, ExceptionLevel el); +SecurityState securityStateAtEL(ThreadContext *tc, ExceptionLevel el); bool longDescFormatInUse(ThreadContext *tc); From 49ca08b01a4f128d7ea651908b9bf464e2ed0ac5 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 19 Jan 2024 13:20:30 +0000 Subject: [PATCH 2/4] arch-arm: Add isStage2 qualifier to the LongDecriptor We are currently using the LongDecriptor for both stage1 and stage2 translations. There are several cases where the bitfield meaning changes depending on the translation stage. Change-Id: Ic33d9ef225a57fd79ce2b4bf47896aeb6bdd8d9c Signed-off-by: Giacomo Travaglini --- src/arch/arm/table_walker.cc | 2 ++ src/arch/arm/table_walker.hh | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 1ce2f65800..6f4116dbe0 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -843,6 +843,7 @@ TableWalker::processWalkLPAE() currState->longDesc.lookupLevel = start_lookup_level; currState->longDesc.aarch64 = false; currState->longDesc.grainSize = Grain4KB; + currState->longDesc.isStage2 = isStage2; fetchDescriptor( desc_addr, currState->longDesc, @@ -1095,6 +1096,7 @@ TableWalker::processWalkAArch64() currState->longDesc.aarch64 = true; currState->longDesc.grainSize = tg; currState->longDesc.physAddrRange = _physAddrRange; + currState->longDesc.isStage2 = isStage2; fetchDescriptor(desc_addr, currState->longDesc, sizeof(uint64_t), flag, start_lookup_level, diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 5143913f4f..66d5ea3674 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -436,7 +436,7 @@ class TableWalker : public ClockedObject LongDescriptor() : data(0), _dirty(false), aarch64(false), grainSize(Grain4KB), - physAddrRange(0) + physAddrRange(0), isStage2(false) {} /** The raw bits of the entry */ @@ -454,6 +454,8 @@ class TableWalker : public ClockedObject uint8_t physAddrRange; + bool isStage2; + uint8_t* getRawPtr() override { From eb400e773b2d47d0a7fe2ab385e09e453b23a972 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 19 Jan 2024 20:07:36 +0000 Subject: [PATCH 3/4] arch-arm: Remove makeStage2 from TLBIOp Change-Id: I25276e4b5b7c491e69208044ceb193c67ddfd91c Signed-off-by: Giacomo Travaglini --- src/arch/arm/mmu.hh | 2 +- src/arch/arm/tlbi_op.cc | 42 +++++++++++++++++++++++++++++++++++-- src/arch/arm/tlbi_op.hh | 46 ++++------------------------------------- 3 files changed, 45 insertions(+), 45 deletions(-) diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh index 28b43e6a0c..c9e0ff1a2e 100644 --- a/src/arch/arm/mmu.hh +++ b/src/arch/arm/mmu.hh @@ -306,7 +306,7 @@ class MMU : public BaseMMU } if (tlbi_op.stage2Flush()) { - flushStage2(tlbi_op.makeStage2()); + flushStage2(tlbi_op); } } diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc index fdb2a160dc..11d9d0a541 100644 --- a/src/arch/arm/tlbi_op.cc +++ b/src/arch/arm/tlbi_op.cc @@ -301,14 +301,36 @@ DTLBIMVA::matchEntry(TlbEntry* te, vmid_t vmid) const void TLBIIPA::operator()(ThreadContext* tc) { - getMMUPtr(tc)->flushStage2(makeStage2()); + getMMUPtr(tc)->flushStage2(*this); CheckerCPU *checker = tc->getCheckerCpuPtr(); if (checker) { - getMMUPtr(checker)->flushStage2(makeStage2()); + getMMUPtr(checker)->flushStage2(*this); } } +TlbEntry::Lookup +TLBIIPA::lookupGen(vmid_t vmid) const +{ + TlbEntry::Lookup lookup_data; + lookup_data.va = szext<56>(addr); + lookup_data.ignoreAsn = true; + lookup_data.vmid = vmid; + lookup_data.ss = ss; + lookup_data.functional = true; + lookup_data.targetRegime = targetRegime; + lookup_data.mode = BaseMMU::Read; + return lookup_data; +} + +bool +TLBIIPA::matchEntry(TlbEntry* te, vmid_t vmid) const +{ + TlbEntry::Lookup lookup_data = lookupGen(vmid); + + return te->match(lookup_data) && (!lastLevel || !te->partial); +} + bool TLBIRMVA::matchEntry(TlbEntry* te, vmid_t vmid) const { @@ -341,5 +363,21 @@ TLBIRMVAA::matchEntry(TlbEntry* te, vmid_t vmid) const } } +bool +TLBIRIPA::matchEntry(TlbEntry* te, vmid_t vmid) const +{ + TlbEntry::Lookup lookup_data = lookupGen(vmid); + lookup_data.size = rangeSize(); + + auto addr_match = te->match(lookup_data) && (!lastLevel || !te->partial); + if (addr_match) { + return tgMap[rangeData.tg] == te->tg && + (resTLBIttl(rangeData.tg, rangeData.ttl) || + rangeData.ttl == te->lookupLevel); + } else { + return false; + } +} + } // namespace ArmISA } // namespace gem5 diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh index 36bd6c47f5..cb130e8b5e 100644 --- a/src/arch/arm/tlbi_op.hh +++ b/src/arch/arm/tlbi_op.hh @@ -135,12 +135,6 @@ class TLBIALL : public TLBIOp return currentEL == EL2; } - TLBIALL - makeStage2() const - { - return TLBIALL(targetRegime, ss, attr); - } - bool el2Enabled; ExceptionLevel currentEL; }; @@ -190,13 +184,6 @@ class TLBIALLEL : public TLBIOp return targetRegime == TranslationRegime::EL10 || targetRegime == TranslationRegime::EL20; } - - TLBIALLEL - makeStage2() const - { - return TLBIALLEL(targetRegime, ss, attr); - } - }; /** Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions */ @@ -219,12 +206,6 @@ class TLBIVMALL : public TLBIOp return stage2; } - TLBIVMALL - makeStage2() const - { - return TLBIVMALL(targetRegime, ss, false, attr); - } - bool el2Enabled; bool stage2; }; @@ -292,12 +273,6 @@ class TLBIALLN : public TLBIOp { return targetRegime != TranslationRegime::EL2; } - - TLBIALLN - makeStage2() const - { - return TLBIALLN(targetRegime); - } }; /** TLB Invalidate by VA, All ASID */ @@ -429,6 +404,8 @@ class TLBIRange /** TLB Invalidate by Intermediate Physical Address */ class TLBIIPA : public TLBIOp { + protected: + TlbEntry::Lookup lookupGen(vmid_t vmid) const; public: TLBIIPA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, bool last_level, Attr _attr=Attr::None) @@ -437,11 +414,7 @@ class TLBIIPA : public TLBIOp void operator()(ThreadContext* tc) override; - bool - matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override - { - panic("This shouldn't be called\n"); - } + bool matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override; bool stage1Flush() const override @@ -449,13 +422,6 @@ class TLBIIPA : public TLBIOp return false; } - /** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */ - virtual TLBIMVAA - makeStage2() const - { - return TLBIMVAA(targetRegime, ss, addr, lastLevel, attr); - } - Addr addr; bool lastLevel; }; @@ -496,11 +462,7 @@ class TLBIRIPA : public TLBIRange, public TLBIIPA TLBIIPA(_target_regime, _ss, startAddress(), last_level, _attr) {} - virtual TLBIMVAA - makeStage2() const - { - return TLBIRMVAA(targetRegime, ss, rangeData, lastLevel, attr); - } + bool matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override; }; } // namespace ArmISA From f3e3c60805a78147e5ab4e5f3f19aed008aa227d Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 18 Jan 2024 17:02:32 +0000 Subject: [PATCH 4/4] arch-arm: Proper support for NonSecure IPA space in Secure state Change-Id: Ie2e2278ecdc5213db74999e3561b2918937c2c2e Signed-off-by: Giacomo Travaglini --- src/arch/arm/insts/misc64.cc | 15 ++----------- src/arch/arm/mmu.cc | 17 +++++++++----- src/arch/arm/mmu.hh | 6 +++-- src/arch/arm/pagetable.hh | 4 ++++ src/arch/arm/regs/misc_types.hh | 4 ++++ src/arch/arm/stage2_lookup.cc | 4 ++-- src/arch/arm/stage2_lookup.hh | 4 +++- src/arch/arm/table_walker.cc | 24 +++++++++++++++----- src/arch/arm/table_walker.hh | 15 +++++++++++-- src/arch/arm/tlbi_op.cc | 10 +++++---- src/arch/arm/tlbi_op.hh | 39 +++++++++++++++++++++++++++++---- src/arch/arm/types.hh | 7 ++++++ 12 files changed, 110 insertions(+), 39 deletions(-) diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index cc149dd676..4ad44bfc63 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -339,14 +339,7 @@ TlbiOp64::tlbiIpaS2(ThreadContext *tc, RegVal value, bool last_level, TlbiAttr attrs) { if (EL2Enabled(tc)) { - if (ss == SecurityState::Secure && bits(value, 63)) { - ss = SecurityState::NonSecure; - } - - const int top_bit = ArmSystem::physAddrRange(tc) == 52 ? - 39 : 35; - TLBIIPA tlbi_op(TranslationRegime::EL10, ss, - static_cast(bits(value, top_bit, 0)) << 12, + TLBIIPA tlbi_op(tc, TranslationRegime::EL10, ss, value, last_level, attrs); if (shareable) { @@ -398,11 +391,7 @@ TlbiOp64::tlbiRipaS2(ThreadContext *tc, RegVal value, bool last_level, TlbiAttr attrs) { if (EL2Enabled(tc)) { - if (ss == SecurityState::Secure && bits(value, 63)) { - ss = SecurityState::NonSecure; - } - - TLBIRIPA tlbi_op(TranslationRegime::EL10, ss, value, + TLBIRIPA tlbi_op(tc, TranslationRegime::EL10, ss, value, last_level, attrs); if (shareable) { diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc index 3df8b9356c..d349455c3b 100644 --- a/src/arch/arm/mmu.cc +++ b/src/arch/arm/mmu.cc @@ -1385,11 +1385,11 @@ MMU::tranTypeEL(CPSR cpsr, SCR scr, ArmTranslationType type) Fault MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, - SecurityState ss, ArmTranslationType tran_type, + SecurityState ss, PASpace ipaspace, ArmTranslationType tran_type, bool stage2) { return getTE(te, req, tc, mode, translation, timing, functional, - ss, tran_type, stage2 ? s2State : s1State); + ss, ipaspace, tran_type, stage2 ? s2State : s1State); } TlbEntry* @@ -1416,7 +1416,7 @@ MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, SecurityState ss, Fault MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, - SecurityState ss, ArmTranslationType tran_type, + SecurityState ss, PASpace ipaspace, ArmTranslationType tran_type, CachedState& state) { // In a 2-stage system, the IPA->PA translation can be started via this @@ -1459,7 +1459,7 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, fault = getTableWalker(mode, state.isStage2)->walk( req, tc, state.asid, state.vmid, mode, translation, timing, functional, ss, - tran_type, state.stage2DescReq, *te); + ipaspace, tran_type, state.stage2DescReq, *te); // for timing mode, return and wait for table walk, if (timing || fault != NoFault) { @@ -1482,12 +1482,16 @@ MMU::getResultTe(TlbEntry **te, const RequestPtr &req, Fault fault; if (state.isStage2) { + PASpace ipaspace = state.securityState == SecurityState::Secure ? + PASpace::Secure : PASpace::NonSecure; + // We are already in the stage 2 TLB. Grab the table entry for stage // 2 only. We are here because stage 1 translation is disabled. TlbEntry *s2_te = nullptr; // Get the stage 2 table entry fault = getTE(&s2_te, req, tc, mode, translation, timing, functional, - state.securityState, state.curTranType, state); + state.securityState, ipaspace, + state.curTranType, state); // Check permissions of stage 2 if (isCompleteTranslation(s2_te) && (fault == NoFault)) { if (state.aarch64) @@ -1505,7 +1509,8 @@ MMU::getResultTe(TlbEntry **te, const RequestPtr &req, // Get the stage 1 table entry fault = getTE(&s1_te, req, tc, mode, translation, timing, functional, - state.securityState, state.curTranType, state); + state.securityState, PASpace::NonSecure, + state.curTranType, state); // only proceed if we have a valid table entry if (isCompleteTranslation(s1_te) && (fault == NoFault)) { // Check stage 1 permissions before checking stage 2 diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh index c9e0ff1a2e..46d904278a 100644 --- a/src/arch/arm/mmu.hh +++ b/src/arch/arm/mmu.hh @@ -412,12 +412,14 @@ class MMU : public BaseMMU Fault getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, - SecurityState ss, ArmTranslationType tran_type, + SecurityState ss, PASpace ipaspace, + ArmTranslationType tran_type, bool stage2); Fault getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, - SecurityState ss, ArmTranslationType tran_type, + SecurityState ss, PASpace ipaspace, + ArmTranslationType tran_type, CachedState &state); Fault getResultTe(TlbEntry **te, const RequestPtr &req, diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh index ab17b3df0d..8a3f7943d5 100644 --- a/src/arch/arm/pagetable.hh +++ b/src/arch/arm/pagetable.hh @@ -241,6 +241,8 @@ struct TlbEntry : public Serializable bool ns; // Security state of the translation regime SecurityState ss; + // IPA Space (stage2 entries only) + PASpace ipaSpace; // Translation regime on insert, AARCH64 EL0&1, AARCH32 -> el=1 TranslationRegime regime; // This is used to distinguish between instruction and data entries @@ -272,6 +274,7 @@ struct TlbEntry : public Serializable domain(DomainType::Client), mtype(MemoryType::StronglyOrdered), longDescFormat(false), global(false), valid(true), ns(true), ss(SecurityState::NonSecure), + ipaSpace(PASpace::NonSecure), regime(TranslationRegime::EL10), type(TypeTLB::unified), partial(false), nonCacheable(uncacheable), @@ -292,6 +295,7 @@ struct TlbEntry : public Serializable domain(DomainType::Client), mtype(MemoryType::StronglyOrdered), longDescFormat(false), global(false), valid(false), ns(true), ss(SecurityState::NonSecure), + ipaSpace(PASpace::NonSecure), regime(TranslationRegime::EL10), type(TypeTLB::unified), partial(false), nonCacheable(false), shareable(false), outerShareable(false), xn(0), pxn(0), diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index 5bb3b59847..171d80e511 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -655,6 +655,10 @@ namespace ArmISA Bitfield<19> vs; // Only defined for VTCR_EL2 Bitfield<21> ha; // Only defined for VTCR_EL2 Bitfield<22> hd; // Only defined for VTCR_EL2 + Bitfield<29> nsw; // Only defined for VTCR_EL2 + Bitfield<29> sw; // Only defined for VSTCR_EL2 + Bitfield<30> nsa; // Only defined for VTCR_EL2 + Bitfield<30> sa; // Only defined for VSTCR_EL2 EndBitUnion(VTCR_t) BitUnion32(PRRR) diff --git a/src/arch/arm/stage2_lookup.cc b/src/arch/arm/stage2_lookup.cc index febfd60fee..7c3bf8421c 100644 --- a/src/arch/arm/stage2_lookup.cc +++ b/src/arch/arm/stage2_lookup.cc @@ -57,7 +57,7 @@ Fault Stage2LookUp::getTe(ThreadContext *tc, TlbEntry *destTe) { fault = mmu->getTE(&stage2Te, req, tc, mode, this, timing, - functional, ss, tranType, true); + functional, ss, ipaSpace, tranType, true); // Call finish if we're done already if ((fault != NoFault) || (stage2Te != NULL)) { @@ -193,7 +193,7 @@ Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req, if ((fault == NoFault) && (stage2Te == NULL)) { // OLD_LOOK: stage2Tlb fault = mmu->getTE(&stage2Te, req, tc, mode, this, - timing, functional, ss, tranType, true); + timing, functional, ss, ipaSpace, tranType, true); } // Now we have the stage 2 table entry we need to merge it with the stage diff --git a/src/arch/arm/stage2_lookup.hh b/src/arch/arm/stage2_lookup.hh index 2192e244be..c6701ab013 100644 --- a/src/arch/arm/stage2_lookup.hh +++ b/src/arch/arm/stage2_lookup.hh @@ -73,6 +73,7 @@ class Stage2LookUp : public BaseMMU::Translation bool complete; bool selfDelete; SecurityState ss; + PASpace ipaSpace; public: Stage2LookUp(MMU *_mmu, TlbEntry s1_te, const RequestPtr &_req, @@ -82,7 +83,8 @@ class Stage2LookUp : public BaseMMU::Translation : mmu(_mmu), stage1Te(s1_te), s1Req(_req), transState(_transState), mode(_mode), timing(_timing), functional(_functional), tranType(_tranType), stage2Te(nullptr), - fault(NoFault), complete(false), selfDelete(false), ss(_ss) + fault(NoFault), complete(false), selfDelete(false), ss(_ss), + ipaSpace(s1_te.ns ? PASpace::NonSecure : PASpace::Secure) { req = std::make_shared(); req->setVirt(s1_te.pAddr(s1Req->getVaddr()), s1Req->getSize(), diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 6f4116dbe0..81111cddd6 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -295,7 +295,8 @@ Fault TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, vmid_t _vmid, MMU::Mode _mode, MMU::Translation *_trans, bool _timing, bool _functional, - SecurityState ss, MMU::ArmTranslationType tranType, + SecurityState ss, PASpace ipaspace, + MMU::ArmTranslationType tranType, bool _stage2Req, const TlbEntry *walk_entry) { assert(!(_functional && _timing)); @@ -344,6 +345,7 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, if (isStage2) { currState->regime = TranslationRegime::EL10; currState->aarch64 = ELIs64(_tc, EL2); + currState->ipaSpace = ipaspace; } else { currState->regime = translationRegime(_tc, currState->el); @@ -382,7 +384,8 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2); if (isStage2) { currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); - if (currState->secureLookup) { + if (currState->ss == SecurityState::Secure && + currState->ipaSpace == PASpace::Secure) { currState->vtcr = currState->tc->readMiscReg(MISCREG_VSTCR_EL2); } else { @@ -905,12 +908,19 @@ TableWalker::processWalkAArch64() switch (currState->regime) { case TranslationRegime::EL10: if (isStage2) { - if (currState->secureLookup) { + if (currState->ss == SecurityState::Secure && + currState->ipaSpace == PASpace::Secure) { + // Secure EL1&0 Secure IPA DPRINTF(TLB, " - Selecting VSTTBR_EL2 (AArch64 stage 2)\n"); ttbr = currState->tc->readMiscReg(MISCREG_VSTTBR_EL2); + currState->secureLookup = !currState->vtcr.sw; } else { + // Secure EL1&0 NonSecure IPA or NonSecure EL1&0 DPRINTF(TLB, " - Selecting VTTBR_EL2 (AArch64 stage 2)\n"); ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2); + currState->secureLookup = currState->ss == SecurityState::Secure ? + !currState->vtcr.nsw : // Secure EL1&0 NonSecure IPA + false; // NonSecure EL1&0 } tsz = 64 - currState->vtcr.t0sz64; tg = GrainMap_tg0[currState->vtcr.tg0]; @@ -1809,8 +1819,10 @@ TableWalker::doLongDescriptor() case LongDescriptor::Table: { // Set hierarchical permission flags - currState->secureLookup = currState->secureLookup && - currState->longDesc.secureTable(); + if (!isStage2) { + currState->secureLookup = currState->secureLookup && + currState->longDesc.secureTable(); + } currState->longDescData->rwTable = currState->longDescData->rwTable && (currState->longDesc.rwTable() || currState->hpd); @@ -2246,6 +2258,7 @@ TableWalker::insertPartialTableEntry(LongDescriptor &descriptor) te.lookupLevel = descriptor.lookupLevel; te.ns = !descriptor.secure(have_security, currState); te.ss = currState->ss; + te.ipaSpace = currState->ipaSpace; // Used by stage2 entries only te.type = TypeTLB::unified; te.regime = currState->regime; @@ -2292,6 +2305,7 @@ TableWalker::insertTableEntry(DescriptorBase &descriptor, bool long_descriptor) te.lookupLevel = descriptor.lookupLevel; te.ns = !descriptor.secure(have_security, currState); te.ss = currState->ss; + te.ipaSpace = currState->ipaSpace; // Used by stage2 entries only te.xn = descriptor.xn(); te.type = currState->mode == BaseMMU::Execute ? TypeTLB::instruction : TypeTLB::data; diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 66d5ea3674..f391a4f1fd 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -493,8 +493,13 @@ class TableWalker : public ClockedObject secure(bool have_security, WalkerState *currState) const override { if (type() == Block || type() == Page) { - return have_security && - (currState->secureLookup && !bits(data, 5)); + if (isStage2) { + return have_security && currState->secureLookup && + !currState->vtcr.nsa; + } else { + return have_security && + (currState->secureLookup && !bits(data, 5)); + } } else { return have_security && currState->secureLookup; } @@ -906,6 +911,11 @@ class TableWalker : public ClockedObject * long descriptor table attributes. */ bool secureLookup = false; + /** IPA space (Secure vs NonSecure); stage2 only. + * This depends on whether the stage1 translation targeted + * a secure or non-secure IPA space */ + PASpace ipaSpace; + /** True if table walks are uncacheable (for table descriptors) */ bool isUncacheable; @@ -1143,6 +1153,7 @@ class TableWalker : public ClockedObject uint16_t asid, vmid_t _vmid, BaseMMU::Mode mode, BaseMMU::Translation *_trans, bool timing, bool functional, SecurityState ss, + PASpace ipaspace, MMU::ArmTranslationType tran_type, bool stage2, const TlbEntry *walk_entry); diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc index 11d9d0a541..40a4e8d8c2 100644 --- a/src/arch/arm/tlbi_op.cc +++ b/src/arch/arm/tlbi_op.cc @@ -328,7 +328,8 @@ TLBIIPA::matchEntry(TlbEntry* te, vmid_t vmid) const { TlbEntry::Lookup lookup_data = lookupGen(vmid); - return te->match(lookup_data) && (!lastLevel || !te->partial); + return te->match(lookup_data) && (!lastLevel || !te->partial) && + ipaSpace == te->ipaSpace; } bool @@ -371,9 +372,10 @@ TLBIRIPA::matchEntry(TlbEntry* te, vmid_t vmid) const auto addr_match = te->match(lookup_data) && (!lastLevel || !te->partial); if (addr_match) { - return tgMap[rangeData.tg] == te->tg && - (resTLBIttl(rangeData.tg, rangeData.ttl) || - rangeData.ttl == te->lookupLevel); + return ipaSpace == te->ipaSpace && + tgMap[rangeData.tg] == te->tg && + (resTLBIttl(rangeData.tg, rangeData.ttl) || + rangeData.ttl == te->lookupLevel); } else { return false; } diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh index cb130e8b5e..20d31a7e25 100644 --- a/src/arch/arm/tlbi_op.hh +++ b/src/arch/arm/tlbi_op.hh @@ -409,9 +409,37 @@ class TLBIIPA : public TLBIOp public: TLBIIPA(TranslationRegime _target_regime, SecurityState _ss, Addr _addr, bool last_level, Attr _attr=Attr::None) - : TLBIOp(_target_regime, _ss, _attr), addr(_addr), lastLevel(last_level) + : TLBIOp(_target_regime, _ss, _attr), + addr(_addr), + lastLevel(last_level), + ipaSpace(PASpace::NonSecure) {} + TLBIIPA(ThreadContext *tc, TranslationRegime _target_regime, + SecurityState _ss, RegVal val, + bool last_level, Attr _attr=Attr::None) + : TLBIOp(_target_regime, _ss, _attr), + addr(0), + lastLevel(last_level), + ipaSpace(PASpace::NonSecure) + { + const int top_bit = ArmSystem::physAddrRange(tc) == 52 ? + 39 : 35; + addr = static_cast(bits(val, top_bit, 0)) << 12; + + switch (ss) { + case SecurityState::NonSecure: + ipaSpace = PASpace::NonSecure; + break; + case SecurityState::Secure: + ipaSpace = bits(val, 63) ? + PASpace::NonSecure : PASpace::Secure; + break; + default: + panic("Invalid SecurityState\n"); + } + } + void operator()(ThreadContext* tc) override; bool matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override; @@ -424,6 +452,7 @@ class TLBIIPA : public TLBIOp Addr addr; bool lastLevel; + PASpace ipaSpace; }; /** TLB Range Invalidate by VA */ @@ -456,11 +485,13 @@ class TLBIRMVAA : public TLBIRange, public TLBIMVAA class TLBIRIPA : public TLBIRange, public TLBIIPA { public: - TLBIRIPA(TranslationRegime _target_regime, SecurityState _ss, + TLBIRIPA(ThreadContext *tc, TranslationRegime _target_regime, SecurityState _ss, RegVal val, bool last_level, Attr _attr) : TLBIRange(val), - TLBIIPA(_target_regime, _ss, startAddress(), last_level, _attr) - {} + TLBIIPA(tc, _target_regime, _ss, val, last_level, _attr) + { + addr = startAddress(); + } bool matchEntry(TlbEntry *entry, vmid_t curr_vmid) const override; }; diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 86c632c498..d0a578a524 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -275,6 +275,13 @@ namespace ArmISA Secure }; + /** Physical Address Space */ + enum class PASpace + { + NonSecure, + Secure + }; + enum ExceptionLevel { EL0 = 0,