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Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem

Browse Source 
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
This commit is contained in:
Korey Sewell
2006-07-23 13:41:53 -04:00
parent f9729e999f 19ca97af79
commit 6e969c31c7
49 changed files with 2127 additions and 155 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/alpha/isa/mem.isa
View File

@@ -668,7 +668,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ completeAccTemplate.subst(completeacc_iop))
}};
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \

34
src/arch/mips/faults.cc
View File

@@ -25,13 +25,15 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
* Authors: Gabe Black
* Korey Sewell
*/
#include "arch/mips/faults.hh"
#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
#if !FULL_SYSTEM
#include "sim/process.hh"
#include "mem/page_table.hh"
@@ -110,35 +112,6 @@ FaultName IntegerOverflowFault::_name = "intover";
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
#if FULL_SYSTEM
void MipsFault::invoke(ThreadContext * tc)
{
FaultBase::invoke(tc);
countStat()++;
// exception restart address
if (setRestartAddress() || !tc->inPalMode())
tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC());
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
tc->setMiscReg(MipsISA::IPR_EXC_ADDR,
tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
}
tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
tc->setNextPC(tc->readPC() + sizeof(MachInst));
}
void ArithmeticFault::invoke(ThreadContext * tc)
{
FaultBase::invoke(tc);
panic("Arithmetic traps are unimplemented!");
}
#else //!FULL_SYSTEM
void PageTableFault::invoke(ThreadContext *tc)
{
Process *p = tc->getProcessPtr();
@@ -159,6 +132,5 @@ void PageTableFault::invoke(ThreadContext *tc)
}
}
#endif
} // namespace MipsISA

3
src/arch/mips/faults.hh
View File

@@ -25,7 +25,8 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
* Authors: Gabe Black
* Korey Sewell
*/
#ifndef __MIPS_FAULTS_HH__

2
src/arch/mips/isa/decoder.isa
View File

@@ -1089,7 +1089,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
{{ uint64_t tmp = write_result;
Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
}}, mem_flags=LOCKED);
}}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
format StoreMemory {
0x1: swc1({{ Mem.uw = Ft.uw; }});

5
src/arch/mips/isa/formats/basic.isa
View File

@@ -26,7 +26,8 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Korey Sewell
// Authors: Steve Reinhardt
// Korey Sewell
// Declarations for execute() methods.
def template BasicExecDeclare {{
@@ -85,7 +86,7 @@ def template BasicDecodeWithMnemonic {{
return new %(class_name)s("%(mnemonic)s", machInst);
}};
// The most basic instruction format... used only for a few misc. insts
// The most basic instruction format...
def format BasicOp(code, *flags) {{
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)

5
src/arch/mips/isa/formats/branch.isa
View File

@@ -235,10 +235,11 @@ def format Branch(code,*opt_flags) {{
else:
inst_flags += (x, )
#Take into account uncond. branch instruction
if 'cond == 1' in code:
inst_flags += ('IsCondControl', )
inst_flags += ('IsUnCondControl', )
else:
inst_flags += ('IsUncondControl', )
inst_flags += ('IsCondControl', )
#Condition code
code = 'bool cond;\n' + code

42
src/arch/mips/isa/formats/mem.isa
View File

@@ -26,7 +26,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
// Authors: Steve Reinhardt
// Korey Sewell
////////////////////////////////////////////////////////////////////
@@ -162,7 +162,7 @@ def template InitiateAccDeclare {{
def template CompleteAccDeclare {{
Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
@@ -288,7 +288,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(uint8_t *data,
Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -297,7 +297,7 @@ def template LoadCompleteAcc {{
%(fp_enable_check)s;
%(op_decl)s;
memcpy(&Mem, data, sizeof(Mem));
Mem = pkt->get<typeof(Mem)>();
if (fault == NoFault) {
%(memacc_code)s;
@@ -390,7 +390,6 @@ def template StoreInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
@@ -403,7 +402,7 @@ def template StoreInitiateAcc {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
memAccessFlags, NULL);
if (traceData) { traceData->setData(Mem); }
}
@@ -413,17 +412,38 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(uint8_t *data,
Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_dest_decl)s;
memcpy(&write_result, data, sizeof(write_result));
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template StoreCondCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_dest_decl)s;
uint64_t write_result = pkt->req->getScResult();
if (fault == NoFault) {
%(postacc_code)s;
@@ -489,7 +509,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
Fault %(class_name)s::completeAcc(uint8_t *data,
Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -580,5 +600,5 @@ def format StoreCond(memacc_code, postacc_code,
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
postacc_code, exec_template_base = 'Store')
postacc_code, exec_template_base = 'StoreCond')
}};

12
src/arch/mips/isa/formats/util.isa
View File

@@ -65,7 +65,7 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
if (exec_template_base == 'Load'):
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
completeacc_cblk = CodeBlock(memacc_code + postacc_code)
elif (exec_template_base == 'Store'):
elif (exec_template_base.startswith('Store')):
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
completeacc_cblk = CodeBlock(postacc_code)
else:
@@ -83,7 +83,7 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
initiateacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.postacc_code = postacc_cblk.code
elif (exec_template_base == 'Store'):
elif (exec_template_base.startswith('Store')):
initiateacc_iop.ea_code = ea_cblk.code
initiateacc_iop.memacc_code = memacc_cblk.code
completeacc_iop.postacc_code = postacc_cblk.code
@@ -104,6 +104,13 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
memacc_iop.constructor += s
# select templates
# define aliases... most StoreCond templates are the same as the
# corresponding Store templates (only CompleteAcc is different).
StoreCondMemAccExecute = StoreMemAccExecute
StoreCondExecute = StoreExecute
StoreCondInitiateAcc = StoreInitiateAcc
memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
fullExecTemplate = eval(exec_template_base + 'Execute')
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
@@ -118,7 +125,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ initiateAccTemplate.subst(initiateacc_iop)
+ completeAccTemplate.subst(completeacc_iop))
}};
output header {{
std::string inst2string(MachInst machInst);
}};

8
src/arch/mips/isa_traits.cc
View File

@@ -73,9 +73,9 @@ void
RegFile::serialize(std::ostream &os)
{
intRegFile.serialize(os);
//SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
//SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
//SERIALZE_ARRAY(miscRegFile);
//SERIALIZE_SCALAR(miscRegs.fpcr);
//SERIALIZE_SCALAR(miscRegs.uniq);
//SERIALIZE_SCALAR(miscRegs.lock_flag);
//SERIALIZE_SCALAR(miscRegs.lock_addr);
SERIALIZE_SCALAR(pc);
@@ -88,9 +88,9 @@ void
RegFile::unserialize(Checkpoint *cp, const std::string &section)
{
intRegFile.unserialize(cp, section);
//UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
//UNSERIALIZE_ARRAY(floatRegFile);
//UNSERIALZE_ARRAY(miscRegFile);
//UNSERIALIZE_SCALAR(miscRegs.fpcr);
//UNSERIALIZE_SCALAR(miscRegs.uniq);
//UNSERIALIZE_SCALAR(miscRegs.lock_flag);
//UNSERIALIZE_SCALAR(miscRegs.lock_addr);
UNSERIALIZE_SCALAR(pc);

5
src/arch/mips/process.cc
View File

@@ -41,8 +41,6 @@
using namespace std;
using namespace MipsISA;
Addr MipsLiveProcess::stack_start = 0x7FFFFFFF;
MipsLiveProcess::MipsLiveProcess(const std::string &nm, ObjectFile *objFile,
System *_system, int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv, std::vector<std::string> &envp)
@@ -51,11 +49,10 @@ MipsLiveProcess::MipsLiveProcess(const std::string &nm, ObjectFile *objFile,
{
// Set up stack. On MIPS, stack starts at the top of kuseg
// user address space. MIPS stack grows down from here
stack_base = stack_start;
stack_base = 0x7FFFFFFF;
// Set pointer for next thread stack. Reserve 8M for main stack.
next_thread_stack_base = stack_base - (8 * 1024 * 1024);
stack_start = next_thread_stack_base;
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();

2
src/arch/mips/process.hh
View File

@@ -51,8 +51,6 @@ class MipsLiveProcess : public LiveProcess
void startup();
static Addr stack_start;
};

13
src/arch/mips/regfile/misc_regfile.hh
View File

@@ -45,12 +45,25 @@ namespace MipsISA
protected:
uint64_t fpcr; // floating point condition codes
// FPCR is not used in MIPS. Condition
// codes are kept as part of the FloatRegFile
bool lock_flag; // lock flag for LL/SC
// use LL reg. in the future
Addr lock_addr; // lock address for LL/SC
// use LLAddr reg. in the future
MiscReg miscRegFile[NumMiscRegs];
public:
void clear()
{
fpcr = 0;
lock_flag = 0;
lock_addr = 0;
}
void copyMiscRegs(ThreadContext *tc);
MiscReg readReg(int misc_reg)