diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index 397711c09a..a350319258 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -64,7 +64,7 @@ class BasePrefetcher(ClockedObject): abstract = True cxx_class = "gem5::prefetch::Base" cxx_header = "mem/cache/prefetch/base.hh" - cxx_exports = [PyBindMethod("addEventProbe"), PyBindMethod("addTLB")] + cxx_exports = [PyBindMethod("addEventProbe"), PyBindMethod("addMMU")] sys = Param.System(Parent.any, "System this prefetcher belongs to") # Get the block size from the parent (system) @@ -93,7 +93,7 @@ class BasePrefetcher(ClockedObject): def __init__(self, **kwargs): super().__init__(**kwargs) self._events = [] - self._tlbs = [] + self._mmus = [] def addEvent(self, newObject): self._events.append(newObject) @@ -101,8 +101,8 @@ class BasePrefetcher(ClockedObject): # Override the normal SimObject::regProbeListeners method and # register deferred event handlers. def regProbeListeners(self): - for tlb in self._tlbs: - self.getCCObject().addTLB(tlb.getCCObject()) + for mmu in self._mmus: + self.getCCObject().addMMU(mmu.getCCObject()) for event in self._events: event.register() self.getCCObject().regProbeListeners() @@ -114,10 +114,10 @@ class BasePrefetcher(ClockedObject): raise TypeError("probeNames must have at least one element") self.addEvent(HWPProbeEvent(self, simObj, *probeNames)) - def registerTLB(self, simObj): + def registerMMU(self, simObj): if not isinstance(simObj, SimObject): raise TypeError("argument must be a SimObject type") - self._tlbs.append(simObj) + self._mmus.append(simObj) class MultiPrefetcher(BasePrefetcher): diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index cb4c1e8118..9ff81fba68 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -103,7 +103,7 @@ Base::Base(const BasePrefetcherParams &p) prefetchOnPfHit(p.prefetch_on_pf_hit), useVirtualAddresses(p.use_virtual_addresses), prefetchStats(this), issuedPrefetches(0), - usefulPrefetches(0), tlb(nullptr) + usefulPrefetches(0), mmu(nullptr) { } @@ -299,10 +299,10 @@ Base::addEventProbe(SimObject *obj, const char *name) } void -Base::addTLB(BaseTLB *t) +Base::addMMU(BaseMMU *m) { - fatal_if(tlb != nullptr, "Only one TLB can be registered"); - tlb = t; + fatal_if(mmu != nullptr, "Only one MMU can be registered"); + mmu = m; } } // namespace prefetch diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh index f2a8207d35..e5e43e534f 100644 --- a/src/mem/cache/prefetch/base.hh +++ b/src/mem/cache/prefetch/base.hh @@ -364,8 +364,8 @@ class Base : public ClockedObject /** Total prefetches that has been useful */ uint64_t usefulPrefetches; - /** Registered tlb for address translations */ - BaseTLB * tlb; + /** Registered mmu for address translations */ + BaseMMU * mmu; public: Base(const BasePrefetcherParams &p); @@ -437,12 +437,12 @@ class Base : public ClockedObject void addEventProbe(SimObject *obj, const char *name); /** - * Add a BaseTLB object to be used whenever a translation is needed. + * Add a BaseMMU object to be used whenever a translation is needed. * This is generally required when the prefetcher is allowed to generate * page crossing references and/or uses virtual addresses for training. - * @param tlb pointer to the BaseTLB object to add + * @param mmu pointer to the BaseMMU object to add */ - void addTLB(BaseTLB *tlb); + void addMMU(BaseMMU *mmu); }; } // namespace prefetch diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc index da9cbf479e..b85a227f00 100644 --- a/src/mem/cache/prefetch/queued.cc +++ b/src/mem/cache/prefetch/queued.cc @@ -78,13 +78,13 @@ Queued::DeferredPacket::createPkt(Addr paddr, unsigned blk_size, } void -Queued::DeferredPacket::startTranslation(BaseTLB *tlb) +Queued::DeferredPacket::startTranslation(BaseMMU *mmu) { assert(translationRequest != nullptr); if (!ongoingTranslation) { ongoingTranslation = true; // Prefetchers only operate in Timing mode - tlb->translateTiming(translationRequest, tc, this, BaseMMU::Read); + mmu->translateTiming(translationRequest, tc, this, BaseMMU::Read); } } @@ -216,7 +216,7 @@ Queued::notify(const PacketPtr &pkt, const PrefetchInfo &pfi) } } - bool can_cross_page = (tlb != nullptr); + bool can_cross_page = (mmu != nullptr); if (can_cross_page || samePage(addr_prio.first, pfi.getAddr())) { PrefetchInfo new_pfi(pfi,addr_prio.first); statsQueued.pfIdentified++; @@ -293,7 +293,7 @@ Queued::processMissingTranslations(unsigned max) // Increase the iterator first because dp.startTranslation can end up // calling finishTranslation, which will erase "it" it++; - dp.startTranslation(tlb); + dp.startTranslation(mmu); count += 1; } } @@ -311,7 +311,7 @@ Queued::translationComplete(DeferredPacket *dp, bool failed) assert(it != pfqMissingTranslation.end()); if (!failed) { DPRINTF(HWPrefetch, "%s Translation of vaddr %#x succeeded: " - "paddr %#x \n", tlb->name(), + "paddr %#x \n", mmu->name(), it->translationRequest->getVaddr(), it->translationRequest->getPaddr()); Addr target_paddr = it->translationRequest->getPaddr(); @@ -329,7 +329,7 @@ Queued::translationComplete(DeferredPacket *dp, bool failed) } } else { DPRINTF(HWPrefetch, "%s Translation of vaddr %#x failed, dropping " - "prefetch request %#x \n", tlb->name(), + "prefetch request %#x \n", mmu->name(), it->translationRequest->getVaddr()); } pfqMissingTranslation.erase(it); diff --git a/src/mem/cache/prefetch/queued.hh b/src/mem/cache/prefetch/queued.hh index c769b3875a..87d3456def 100644 --- a/src/mem/cache/prefetch/queued.hh +++ b/src/mem/cache/prefetch/queued.hh @@ -134,10 +134,10 @@ class Queued : public Base ThreadContext *tc, BaseMMU::Mode mode) override; /** - * Issues the translation request to the provided TLB - * @param tlb the tlb that has to translate the address + * Issues the translation request to the provided MMU + * @param mmu the mmu that has to translate the address */ - void startTranslation(BaseTLB *tlb); + void startTranslation(BaseMMU *mmu); }; std::list pfq;