diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f22c58ddd5..820bede1b5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -947,7 +947,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     // hardware transactional memory
 
     SimpleExecContext *t_info = threadInfo[curThread];
-    const bool is_htm_speculative =
+    const bool is_htm_speculative M5_VAR_USED =
         t_info->inHtmTransactionalState();
 
     // received a response from the dcache: complete the load or store