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system-arm: Enabled HDLcd by default in DTS

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This is fine as people using *_hdlcd.dtsi are willing to simulate
an HDLcd

JIRA: https://gem5.atlassian.net/browse/GEM5-866

Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38797
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-01-04 13:48:48 +00:00
parent 1ce08f1655
commit 6dcc7951cf
3 changed files with 4 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
system/arm/dt/platforms/display.dtsi
View File

@@ -55,8 +55,6 @@
}; };
&dp0 { &dp0 {
status = "ok";
port { port {
dp0_output: endpoint@0 { dp0_output: endpoint@0 {
remote-endpoint = <&dp0_virt_input>; remote-endpoint = <&dp0_virt_input>;

9
system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2019 ARM Limited * Copyright (c) 2015-2019, 2021 ARM Limited
* All rights reserved * All rights reserved
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -29,18 +29,13 @@
/include/ "vexpress_gem5_v1_base.dtsi" /include/ "vexpress_gem5_v1_base.dtsi"
/ { / {
/* The display processor needs custom configuration to setup its
* output ports. Disable it by default in the platform until the
* DT bindings have stabilize.
*/
dp0: hdlcd@2b000000 { dp0: hdlcd@2b000000 {
compatible = "arm,hdlcd"; compatible = "arm,hdlcd";
reg = <0x0 0x2b000000 0x0 0x1000>; reg = <0x0 0x2b000000 0x0 0x1000>;
interrupts = <0 63 4>; interrupts = <0 63 4>;
clocks = <&osc_pxl>; clocks = <&osc_pxl>;
clock-names = "pxlclk"; clock-names = "pxlclk";
status = "ok";
status = "disabled";
}; };
}; };

8
system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2019 ARM Limited * Copyright (c) 2015-2019, 2021 ARM Limited
* All rights reserved * All rights reserved
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -29,17 +29,13 @@
/include/ "vexpress_gem5_v2_base.dtsi" /include/ "vexpress_gem5_v2_base.dtsi"
/ { / {
/* The display processor needs custom configuration to setup its
* output ports. Disable it by default in the platform until the
* DT bindings have stabilize.
*/
dp0: hdlcd@2b000000 { dp0: hdlcd@2b000000 {
compatible = "arm,hdlcd"; compatible = "arm,hdlcd";
reg = <0x0 0x2b000000 0x0 0x1000>; reg = <0x0 0x2b000000 0x0 0x1000>;
interrupts = <0 63 4>; interrupts = <0 63 4>;
clocks = <&osc_pxl>; clocks = <&osc_pxl>;
clock-names = "pxlclk"; clock-names = "pxlclk";
status = "disabled"; status = "ok";
}; };
}; };