diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index a9b490d292..1fa4d9e717 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -150,8 +150,6 @@ class BaseCPU(ClockedObject):
     workload = VectorParam.Process([], "processes to run")
 
     mmu = Param.BaseMMU(ArchMMU(), "CPU memory management unit")
-    if buildEnv['TARGET_ISA'] == 'power':
-        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
     interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
     isa = VectorParam.BaseISA([], "ISA instance")