From d8954745cfbe1a1d1ae1b6aec4c3cad0c6e451c8 Mon Sep 17 00:00:00 2001 From: Jarvis Jia Date: Sat, 14 Sep 2024 20:30:48 -0500 Subject: [PATCH 1/2] mem-ruby: Fix replacement policy in GPU_VIPER The current GPU_VIPER protocol's TCC cache update the MRU information twice with calling a_allocateBlock and ut_updateTag which affectgs the LIP and RRIP replacement polies. Remove ut_updateTag fixes the LIP and RRIP replacement polies. --- src/mem/ruby/protocol/GPU_VIPER-TCC.sm | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm index 69a4cb8c73..e39407f0fc 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm @@ -1162,7 +1162,6 @@ machine(MachineType:TCC, "TCC Cache") transition(I, WrVicBlkBack, W) {TagArrayRead, TagArrayWrite, DataArrayWrite} { p_profileMiss; a_allocateBlock; - ut_updateTag; swb_sendWBAck; wdb_writeDirtyBytes; p_popRequestQueue; @@ -1257,7 +1256,6 @@ machine(MachineType:TCC, "TCC Cache") transition(IV, Data, V) {TagArrayRead, TagArrayWrite, DataArrayWrite} { a_allocateBlock; - ut_updateTag; wcb_writeCacheBlock; sdr_sendDataResponse; wada_wakeUpAllDependentsAddr; From 9dfd66aca460f27f31414c22602132cf48067e35 Mon Sep 17 00:00:00 2001 From: Jarvis Jia Date: Sat, 14 Sep 2024 20:30:48 -0500 Subject: [PATCH 2/2] mem-ruby: Fix replacement policy in GPU_VIPER The current GPU_VIPER protocol's TCC cache update the MRU information twice with calling a_allocateBlock and ut_updateTag which affectgs the LIP and RRIP replacement polies. Remove ut_updateTag fixes the LIP and RRIP replacement polies. Change-Id: I79ad9392593e00425a7fe8828048465b2c2c2e1f --- src/mem/ruby/protocol/GPU_VIPER-TCC.sm | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm index 69a4cb8c73..e39407f0fc 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm @@ -1162,7 +1162,6 @@ machine(MachineType:TCC, "TCC Cache") transition(I, WrVicBlkBack, W) {TagArrayRead, TagArrayWrite, DataArrayWrite} { p_profileMiss; a_allocateBlock; - ut_updateTag; swb_sendWBAck; wdb_writeDirtyBytes; p_popRequestQueue; @@ -1257,7 +1256,6 @@ machine(MachineType:TCC, "TCC Cache") transition(IV, Data, V) {TagArrayRead, TagArrayWrite, DataArrayWrite} { a_allocateBlock; - ut_updateTag; wcb_writeCacheBlock; sdr_sendDataResponse; wada_wakeUpAllDependentsAddr;