derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

MEM: Fix residual bus ports and make them master/slave

Browse Source 
This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
This commit is contained in:
Andreas Hansson
2012-02-14 14:15:30 -05:00
parent ac91f90145
commit 6cf9f182f6
6 changed files with 42 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
configs/splash2/cluster.py
View File

@@ -221,19 +221,19 @@ system.l2 = L2(size = options.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
system.physmem.port = system.membus.port
system.l2.cpu_side = system.toL2bus.port
system.l2.mem_side = system.membus.port
system.physmem.port = system.membus.master
system.l2.cpu_side = system.toL2bus.slave
system.l2.mem_side = system.membus.master
# ----------------------
# Connect the L2 cache and clusters together
# ----------------------
for cluster in clusters:
cluster.l1.cpu_side = cluster.clusterbus.port
cluster.l1.mem_side = system.toL2bus.port
cluster.l1.cpu_side = cluster.clusterbus.master
cluster.l1.mem_side = system.toL2bus.slave
for cpu in cluster.cpus:
cpu.icache_port = cluster.clusterbus.port
cpu.dcache_port = cluster.clusterbus.port
cpu.icache_port = cluster.clusterbus.slave
cpu.dcache_port = cluster.clusterbus.slave
# ----------------------
# Define the root

8
configs/splash2/run.py
View File

@@ -207,10 +207,10 @@ system.l2 = L2(size = options.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
system.physmem.port = system.membus.port
system.l2.cpu_side = system.toL2bus.port
system.l2.mem_side = system.membus.port
system.system_port = system.membus.port
system.physmem.port = system.membus.master
system.l2.cpu_side = system.toL2bus.master
system.l2.mem_side = system.membus.slave
system.system_port = system.membus.slave
# ----------------------
# Connect the L2 cache and clusters together