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cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

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Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Fernando Endo
2016-10-15 14:58:45 -05:00
parent 2f5262eb67
commit 6c72c35519
7 changed files with 88 additions and 59 deletions
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4
src/cpu/op_class.hh
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@@ -59,7 +59,9 @@ static const OpClass FloatAddOp = Enums::FloatAdd;
static const OpClass FloatCmpOp = Enums::FloatCmp;
static const OpClass FloatCvtOp = Enums::FloatCvt;
static const OpClass FloatMultOp = Enums::FloatMult;
static const OpClass FloatMultAccOp = Enums::FloatMultAcc;
static const OpClass FloatDivOp = Enums::FloatDiv;
static const OpClass FloatMiscOp = Enums::FloatMisc;
static const OpClass FloatSqrtOp = Enums::FloatSqrt;
static const OpClass SimdAddOp = Enums::SimdAdd;
static const OpClass SimdAddAccOp = Enums::SimdAddAcc;
@@ -83,6 +85,8 @@ static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc;
static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt;
static const OpClass MemReadOp = Enums::MemRead;
static const OpClass MemWriteOp = Enums::MemWrite;
static const OpClass FloatMemReadOp = Enums::FloatMemRead;
static const OpClass FloatMemWriteOp = Enums::FloatMemWrite;
static const OpClass IprAccessOp = Enums::IprAccess;
static const OpClass InstPrefetchOp = Enums::InstPrefetch;
static const OpClass Num_OpClasses = Enums::Num_OpClass;