cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

src/cpu/o3/FuncUnitConfig.py

@@ -68,6 +68,8 @@ class FP_ALU(FUDesc):
 
 class FP_MultDiv(FUDesc):
     opList = [ OpDesc(opClass='FloatMult', opLat=4),
+               OpDesc(opClass='FloatMultAcc', opLat=5),
+               OpDesc(opClass='FloatMisc', opLat=3),
                OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
                OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ]
     count = 2
@@ -96,15 +98,18 @@ class SIMD_Unit(FUDesc):
     count = 4
 
 class ReadPort(FUDesc):
-    opList = [ OpDesc(opClass='MemRead') ]
+    opList = [ OpDesc(opClass='MemRead'),
+               OpDesc(opClass='FloatMemRead') ]
     count = 0
 
 class WritePort(FUDesc):
-    opList = [ OpDesc(opClass='MemWrite') ]
+    opList = [ OpDesc(opClass='MemWrite'),
+               OpDesc(opClass='FloatMemWrite') ]
     count = 0
 
 class RdWrPort(FUDesc):
-    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
+    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'),
+               OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')]
     count = 4
 
 class IprPort(FUDesc):