cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

src/cpu/minor/MinorCPU.py

@@ -142,8 +142,8 @@ class MinorDefaultIntDivFU(MinorFU):
 
 class MinorDefaultFloatSimdFU(MinorFU):
     opClasses = minorMakeOpClassSet([
-        'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv',
-        'FloatSqrt',
+        'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult',
+        'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
         'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
         'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
         'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
@@ -154,7 +154,8 @@ class MinorDefaultFloatSimdFU(MinorFU):
     opLat = 6
 
 class MinorDefaultMemFU(MinorFU):
-    opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite'])
+    opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead',
+                                     'FloatMemWrite'])
     timings = [MinorFUTiming(description='Mem',
         srcRegsRelativeLats=[1], extraAssumedLat=2)]
     opLat = 1