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cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

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Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Fernando Endo
2016-10-15 14:58:45 -05:00
parent 2f5262eb67
commit 6c72c35519
7 changed files with 88 additions and 59 deletions
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6
src/cpu/FuncUnit.py
View File

@@ -43,13 +43,15 @@ from m5.params import *
class OpClass(Enum):
vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatMultAcc', 'FloatDiv',
'FloatMisc', 'FloatSqrt',
'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
'SimdFloatMultAcc', 'SimdFloatSqrt',
'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite',
'IprAccess', 'InstPrefetch']
class OpDesc(SimObject):
type = 'OpDesc'

7
src/cpu/minor/MinorCPU.py
View File

@@ -142,8 +142,8 @@ class MinorDefaultIntDivFU(MinorFU):
class MinorDefaultFloatSimdFU(MinorFU):
opClasses = minorMakeOpClassSet([
'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv',
'FloatSqrt',
'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult',
'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
@@ -154,7 +154,8 @@ class MinorDefaultFloatSimdFU(MinorFU):
opLat = 6
class MinorDefaultMemFU(MinorFU):
opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite'])
opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead',
'FloatMemWrite'])
timings = [MinorFUTiming(description='Mem',
srcRegsRelativeLats=[1], extraAssumedLat=2)]
opLat = 1

11
src/cpu/o3/FuncUnitConfig.py
View File

@@ -68,6 +68,8 @@ class FP_ALU(FUDesc):
class FP_MultDiv(FUDesc):
opList = [ OpDesc(opClass='FloatMult', opLat=4),
OpDesc(opClass='FloatMultAcc', opLat=5),
OpDesc(opClass='FloatMisc', opLat=3),
OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ]
count = 2
@@ -96,15 +98,18 @@ class SIMD_Unit(FUDesc):
count = 4
class ReadPort(FUDesc):
opList = [ OpDesc(opClass='MemRead') ]
opList = [ OpDesc(opClass='MemRead'),
OpDesc(opClass='FloatMemRead') ]
count = 0
class WritePort(FUDesc):
opList = [ OpDesc(opClass='MemWrite') ]
opList = [ OpDesc(opClass='MemWrite'),
OpDesc(opClass='FloatMemWrite') ]
count = 0
class RdWrPort(FUDesc):
opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'),
OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')]
count = 4
class IprPort(FUDesc):

4
src/cpu/op_class.hh
View File

@@ -59,7 +59,9 @@ static const OpClass FloatAddOp = Enums::FloatAdd;
static const OpClass FloatCmpOp = Enums::FloatCmp;
static const OpClass FloatCvtOp = Enums::FloatCvt;
static const OpClass FloatMultOp = Enums::FloatMult;
static const OpClass FloatMultAccOp = Enums::FloatMultAcc;
static const OpClass FloatDivOp = Enums::FloatDiv;
static const OpClass FloatMiscOp = Enums::FloatMisc;
static const OpClass FloatSqrtOp = Enums::FloatSqrt;
static const OpClass SimdAddOp = Enums::SimdAdd;
static const OpClass SimdAddAccOp = Enums::SimdAddAcc;
@@ -83,6 +85,8 @@ static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc;
static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt;
static const OpClass MemReadOp = Enums::MemRead;
static const OpClass MemWriteOp = Enums::MemWrite;
static const OpClass FloatMemReadOp = Enums::FloatMemRead;
static const OpClass FloatMemWriteOp = Enums::FloatMemWrite;
static const OpClass IprAccessOp = Enums::IprAccess;
static const OpClass InstPrefetchOp = Enums::InstPrefetch;
static const OpClass Num_OpClasses = Enums::Num_OpClass;