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cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

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Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Fernando Endo
2016-10-15 14:58:45 -05:00
parent 2f5262eb67
commit 6c72c35519
7 changed files with 88 additions and 59 deletions
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16
src/arch/isa_parser.py
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@@ -1130,9 +1130,21 @@ class InstObjParams(object):
# These are good enough for most cases.
if not self.op_class:
if 'IsStore' in self.flags:
self.op_class = 'MemWriteOp'
# The order matters here: 'IsFloating' and 'IsInteger' are
# usually set in FP instructions because of the base
# register
if 'IsFloating' in self.flags:
self.op_class = 'FloatMemWriteOp'
else:
self.op_class = 'MemWriteOp'
elif 'IsLoad' in self.flags or 'IsPrefetch' in self.flags:
self.op_class = 'MemReadOp'
# The order matters here: 'IsFloating' and 'IsInteger' are
# usually set in FP instructions because of the base
# register
if 'IsFloating' in self.flags:
self.op_class = 'FloatMemReadOp'
else:
self.op_class = 'MemReadOp'
elif 'IsFloating' in self.flags:
self.op_class = 'FloatAddOp'
else: