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cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

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Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Fernando Endo
2016-10-15 14:58:45 -05:00
parent 2f5262eb67
commit 6c72c35519
7 changed files with 88 additions and 59 deletions
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12
configs/common/O3_ARM_v7a.py
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@@ -62,24 +62,28 @@ class O3_ARM_v7a_FP(FUDesc):
OpDesc(opClass='SimdFloatDiv', opLat=3),
OpDesc(opClass='SimdFloatMisc', opLat=3),
OpDesc(opClass='SimdFloatMult', opLat=3),
OpDesc(opClass='SimdFloatMultAcc',opLat=1),
OpDesc(opClass='SimdFloatMultAcc',opLat=5),
OpDesc(opClass='SimdFloatSqrt', opLat=9),
OpDesc(opClass='FloatAdd', opLat=5),
OpDesc(opClass='FloatCmp', opLat=5),
OpDesc(opClass='FloatCvt', opLat=5),
OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
OpDesc(opClass='FloatMult', opLat=4) ]
OpDesc(opClass='FloatMult', opLat=4),
OpDesc(opClass='FloatMultAcc', opLat=5),
OpDesc(opClass='FloatMisc', opLat=3) ]
count = 2
# Load/Store Units
class O3_ARM_v7a_Load(FUDesc):
opList = [ OpDesc(opClass='MemRead',opLat=2) ]
opList = [ OpDesc(opClass='MemRead',opLat=2),
OpDesc(opClass='FloatMemRead',opLat=2) ]
count = 1
class O3_ARM_v7a_Store(FUDesc):
opList = [OpDesc(opClass='MemWrite',opLat=2) ]
opList = [ OpDesc(opClass='MemWrite',opLat=2),
OpDesc(opClass='FloatMemWrite',opLat=2) ]
count = 1
# Functional Units for this CPU