Fix up a few statistics problems.
Stats pretty much line up with old code, except: - bug in old code included L1 latency in L2 miss time, making it too high - UniCoherence did cache-to-cache transfers even from non-owner caches, so occasionally the icache would get a block from the dcache not the L2 - L2 can now receive ReadExReq from L1 since L1s have coherence --HG-- extra : convert_revision : 5052c1a1767b5a662f30a88f16012165a73b791c
This commit is contained in:
Steve Reinhardt
54
src/mem/cache/base_cache.cc
vendored
54
src/mem/cache/base_cache.cc
vendored
@@ -150,20 +150,29 @@ BaseCache::regStats()
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;
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}
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// These macros make it easier to sum the right subset of commands and
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// to change the subset of commands that are considered "demand" vs
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// "non-demand"
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#define SUM_DEMAND(s) \
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(s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq])
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// should writebacks be included here? prior code was inconsistent...
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#define SUM_NON_DEMAND(s) \
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(s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
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demandHits
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.name(name() + ".demand_hits")
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.desc("number of demand (read+write) hits")
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.flags(total)
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;
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demandHits = hits[MemCmd::ReadReq] + hits[MemCmd::WriteReq];
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demandHits = SUM_DEMAND(hits);
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overallHits
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.name(name() + ".overall_hits")
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.desc("number of overall hits")
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.flags(total)
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;
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overallHits = demandHits + hits[MemCmd::SoftPFReq] + hits[MemCmd::HardPFReq]
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+ hits[MemCmd::Writeback];
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overallHits = demandHits + SUM_NON_DEMAND(hits);
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// Miss statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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@@ -183,15 +192,14 @@ BaseCache::regStats()
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.desc("number of demand (read+write) misses")
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.flags(total)
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;
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demandMisses = misses[MemCmd::ReadReq] + misses[MemCmd::WriteReq];
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demandMisses = SUM_DEMAND(misses);
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overallMisses
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.name(name() + ".overall_misses")
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.desc("number of overall misses")
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.flags(total)
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;
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overallMisses = demandMisses + misses[MemCmd::SoftPFReq] +
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misses[MemCmd::HardPFReq] + misses[MemCmd::Writeback];
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overallMisses = demandMisses + SUM_NON_DEMAND(misses);
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// Miss latency statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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@@ -211,15 +219,14 @@ BaseCache::regStats()
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.desc("number of demand (read+write) miss cycles")
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.flags(total)
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;
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demandMissLatency = missLatency[MemCmd::ReadReq] + missLatency[MemCmd::WriteReq];
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demandMissLatency = SUM_DEMAND(missLatency);
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overallMissLatency
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.name(name() + ".overall_miss_latency")
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.desc("number of overall miss cycles")
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.flags(total)
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;
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overallMissLatency = demandMissLatency + missLatency[MemCmd::SoftPFReq] +
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missLatency[MemCmd::HardPFReq];
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overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
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// access formulas
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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@@ -368,15 +375,14 @@ BaseCache::regStats()
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.desc("number of demand (read+write) MSHR hits")
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.flags(total)
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;
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demandMshrHits = mshr_hits[MemCmd::ReadReq] + mshr_hits[MemCmd::WriteReq];
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demandMshrHits = SUM_DEMAND(mshr_hits);
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overallMshrHits
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.name(name() + ".overall_mshr_hits")
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.desc("number of overall MSHR hits")
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.flags(total)
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;
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overallMshrHits = demandMshrHits + mshr_hits[MemCmd::SoftPFReq] +
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mshr_hits[MemCmd::HardPFReq];
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overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
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// MSHR miss statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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@@ -396,15 +402,14 @@ BaseCache::regStats()
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.desc("number of demand (read+write) MSHR misses")
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.flags(total)
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;
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demandMshrMisses = mshr_misses[MemCmd::ReadReq] + mshr_misses[MemCmd::WriteReq];
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demandMshrMisses = SUM_DEMAND(mshr_misses);
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overallMshrMisses
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.name(name() + ".overall_mshr_misses")
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.desc("number of overall MSHR misses")
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.flags(total)
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;
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overallMshrMisses = demandMshrMisses + mshr_misses[MemCmd::SoftPFReq] +
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mshr_misses[MemCmd::HardPFReq];
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overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
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// MSHR miss latency statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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@@ -424,16 +429,15 @@ BaseCache::regStats()
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.desc("number of demand (read+write) MSHR miss cycles")
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.flags(total)
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;
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demandMshrMissLatency = mshr_miss_latency[MemCmd::ReadReq]
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+ mshr_miss_latency[MemCmd::WriteReq];
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demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
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overallMshrMissLatency
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.name(name() + ".overall_mshr_miss_latency")
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.desc("number of overall MSHR miss cycles")
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.flags(total)
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;
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overallMshrMissLatency = demandMshrMissLatency +
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mshr_miss_latency[MemCmd::SoftPFReq] + mshr_miss_latency[MemCmd::HardPFReq];
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overallMshrMissLatency =
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demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
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// MSHR uncacheable statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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@@ -453,9 +457,8 @@ BaseCache::regStats()
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.desc("number of overall MSHR uncacheable misses")
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.flags(total)
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;
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overallMshrUncacheable = mshr_uncacheable[MemCmd::ReadReq]
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+ mshr_uncacheable[MemCmd::WriteReq] + mshr_uncacheable[MemCmd::SoftPFReq]
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+ mshr_uncacheable[MemCmd::HardPFReq];
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overallMshrUncacheable =
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SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
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// MSHR miss latency statistics
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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@@ -475,10 +478,9 @@ BaseCache::regStats()
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.desc("number of overall MSHR uncacheable cycles")
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.flags(total)
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;
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overallMshrUncacheableLatency = mshr_uncacheable_lat[MemCmd::ReadReq]
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+ mshr_uncacheable_lat[MemCmd::WriteReq]
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+ mshr_uncacheable_lat[MemCmd::SoftPFReq]
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+ mshr_uncacheable_lat[MemCmd::HardPFReq];
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overallMshrUncacheableLatency =
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SUM_DEMAND(mshr_uncacheable_lat) +
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SUM_NON_DEMAND(mshr_uncacheable_lat);
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#if 0
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// MSHR access formulas
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