tests,arch-riscv: update bitmanip asmtest binaries (#931)

Gem5 resource update: https://github.com/gem5/gem5-resources/pull/25
Gem5 issue: https://github.com/gem5/gem5/issues/883

Change-Id: I1892d7591d6fa49d0563623fd90292e0d38d9ba3
This commit is contained in:
Yu-Cheng Chang
2024-04-17 00:51:32 +08:00
committed by GitHub
parent 9b463dbdfd
commit 6b4dbdcedb

View File

@@ -69,49 +69,6 @@ rv64_binaries = (
"rv64uamt-ps-amoswap_d", "rv64uamt-ps-amoswap_d",
"rv64uamt-ps-amoxor_d", "rv64uamt-ps-amoxor_d",
"rv64uamt-ps-lrsc_d", "rv64uamt-ps-lrsc_d",
"rv64ub-ps-add_uw",
"rv64ub-ps-andn",
"rv64ub-ps-bclr",
"rv64ub-ps-bclri",
"rv64ub-ps-bext",
"rv64ub-ps-bexti",
"rv64ub-ps-binv",
"rv64ub-ps-binvi",
"rv64ub-ps-bset",
"rv64ub-ps-bseti",
"rv64ub-ps-clmul",
"rv64ub-ps-clmulh",
"rv64ub-ps-clmulr",
"rv64ub-ps-clz",
"rv64ub-ps-clzw",
"rv64ub-ps-cpop",
"rv64ub-ps-cpopw",
"rv64ub-ps-ctz",
"rv64ub-ps-ctzw",
"rv64ub-ps-max",
"rv64ub-ps-maxu",
"rv64ub-ps-min",
"rv64ub-ps-minu",
"rv64ub-ps-orc_b",
"rv64ub-ps-orn",
"rv64ub-ps-rev8",
"rv64ub-ps-rol",
"rv64ub-ps-rolw",
"rv64ub-ps-ror",
"rv64ub-ps-rori",
"rv64ub-ps-roriw",
"rv64ub-ps-rorw",
"rv64ub-ps-sext_b",
"rv64ub-ps-sext_h",
"rv64ub-ps-sh1add",
"rv64ub-ps-sh1add_uw",
"rv64ub-ps-sh2add",
"rv64ub-ps-sh2add_uw",
"rv64ub-ps-sh3add",
"rv64ub-ps-sh3add_uw",
"rv64ub-ps-slli_uw",
"rv64ub-ps-xnor",
"rv64ub-ps-zext_h",
"rv64uc-ps-rvc", "rv64uc-ps-rvc",
"rv64ud-ps-fadd", "rv64ud-ps-fadd",
"rv64ud-ps-fclass", "rv64ud-ps-fclass",
@@ -211,6 +168,49 @@ rv64_binaries = (
"rv64uzfh-ps-ldst", "rv64uzfh-ps-ldst",
"rv64uzfh-ps-move", "rv64uzfh-ps-move",
"rv64uzfh-ps-recoding", "rv64uzfh-ps-recoding",
"rv64uzba-ps-add_uw",
"rv64uzba-ps-sh1add",
"rv64uzba-ps-sh1add_uw",
"rv64uzba-ps-sh2add",
"rv64uzba-ps-sh2add_uw",
"rv64uzba-ps-sh3add",
"rv64uzba-ps-sh3add_uw",
"rv64uzba-ps-slli_uw",
"rv64uzbb-ps-andn",
"rv64uzbb-ps-clz",
"rv64uzbb-ps-clzw",
"rv64uzbb-ps-cpop",
"rv64uzbb-ps-cpopw",
"rv64uzbb-ps-ctz",
"rv64uzbb-ps-ctzw",
"rv64uzbb-ps-max",
"rv64uzbb-ps-maxu",
"rv64uzbb-ps-min",
"rv64uzbb-ps-minu",
"rv64uzbb-ps-orc_b",
"rv64uzbb-ps-orn",
"rv64uzbb-ps-rev8",
"rv64uzbb-ps-rol",
"rv64uzbb-ps-rolw",
"rv64uzbb-ps-ror",
"rv64uzbb-ps-rori",
"rv64uzbb-ps-roriw",
"rv64uzbb-ps-rorw",
"rv64uzbb-ps-sext_b",
"rv64uzbb-ps-sext_h",
"rv64uzbb-ps-xnor",
"rv64uzbb-ps-zext_h",
"rv64uzbc-ps-clmul",
"rv64uzbc-ps-clmulh",
"rv64uzbc-ps-clmulr",
"rv64uzbs-ps-bclr",
"rv64uzbs-ps-bclri",
"rv64uzbs-ps-bext",
"rv64uzbs-ps-bexti",
"rv64uzbs-ps-binv",
"rv64uzbs-ps-binvi",
"rv64uzbs-ps-bset",
"rv64uzbs-ps-bseti",
) )
rv32_binaries = ( rv32_binaries = (
@@ -234,38 +234,6 @@ rv32_binaries = (
"rv32uamt-ps-amoswap_w", "rv32uamt-ps-amoswap_w",
"rv32uamt-ps-amoxor_w", "rv32uamt-ps-amoxor_w",
"rv32uamt-ps-lrsc_w", "rv32uamt-ps-lrsc_w",
"rv32ub-ps-andn",
"rv32ub-ps-bclr",
"rv32ub-ps-bclri",
"rv32ub-ps-bext",
"rv32ub-ps-bexti",
"rv32ub-ps-binv",
"rv32ub-ps-binvi",
"rv32ub-ps-bset",
"rv32ub-ps-bseti",
"rv32ub-ps-clmul",
"rv32ub-ps-clmulh",
"rv32ub-ps-clmulr",
"rv32ub-ps-clz",
"rv32ub-ps-cpop",
"rv32ub-ps-ctz",
"rv32ub-ps-max",
"rv32ub-ps-maxu",
"rv32ub-ps-min",
"rv32ub-ps-minu",
"rv32ub-ps-orc_b",
"rv32ub-ps-orn",
"rv32ub-ps-rev8",
"rv32ub-ps-rol",
"rv32ub-ps-ror",
"rv32ub-ps-rori",
"rv32ub-ps-sext_b",
"rv32ub-ps-sext_h",
"rv32ub-ps-sh1add",
"rv32ub-ps-sh2add",
"rv32ub-ps-sh3add",
"rv32ub-ps-xnor",
"rv32ub-ps-zext_h",
"rv32uc-ps-rvc", "rv32uc-ps-rvc",
"rv32ud-ps-fadd", "rv32ud-ps-fadd",
"rv32ud-ps-fclass", "rv32ud-ps-fclass",
@@ -346,6 +314,38 @@ rv32_binaries = (
"rv32uzfh-ps-ldst", "rv32uzfh-ps-ldst",
"rv32uzfh-ps-move", "rv32uzfh-ps-move",
"rv32uzfh-ps-recoding", "rv32uzfh-ps-recoding",
"rv32uzba-ps-sh1add",
"rv32uzba-ps-sh2add",
"rv32uzba-ps-sh3add",
"rv32uzbb-ps-andn",
"rv32uzbb-ps-clz",
"rv32uzbb-ps-cpop",
"rv32uzbb-ps-ctz",
"rv32uzbb-ps-max",
"rv32uzbb-ps-maxu",
"rv32uzbb-ps-min",
"rv32uzbb-ps-minu",
"rv32uzbb-ps-orc_b",
"rv32uzbb-ps-orn",
"rv32uzbb-ps-rev8",
"rv32uzbb-ps-rol",
"rv32uzbb-ps-ror",
"rv32uzbb-ps-rori",
"rv32uzbb-ps-sext_b",
"rv32uzbb-ps-sext_h",
"rv32uzbb-ps-xnor",
"rv32uzbb-ps-zext_h",
"rv32uzbc-ps-clmul",
"rv32uzbc-ps-clmulh",
"rv32uzbc-ps-clmulr",
"rv32uzbs-ps-bclr",
"rv32uzbs-ps-bclri",
"rv32uzbs-ps-bext",
"rv32uzbs-ps-bexti",
"rv32uzbs-ps-binv",
"rv32uzbs-ps-binvi",
"rv32uzbs-ps-bset",
"rv32uzbs-ps-bseti",
) )
cpu_types = ("atomic", "timing", "minor", "o3") cpu_types = ("atomic", "timing", "minor", "o3")