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Get rid of Packet result field. Error responses are

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now encoded in cmd field.

--HG--
extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
This commit is contained in:
Steve Reinhardt
2007-06-30 10:16:18 -07:00
parent 749126e011
commit 6ab53415ef
35 changed files with 200 additions and 342 deletions
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11
src/dev/alpha/console.cc
View File

@@ -102,7 +102,6 @@ AlphaConsole::read(PacketPtr pkt)
* machine dependent address swizzle is required?
*/
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;
@@ -130,7 +129,7 @@ AlphaConsole::read(PacketPtr pkt)
/* Old console code read in everyting as a 32bit int
* we now break that for better error checking.
*/
pkt->result = Packet::BadAddress;
pkt->setBadAddress();
}
DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
pkt->get<uint32_t>());
@@ -187,17 +186,15 @@ AlphaConsole::read(PacketPtr pkt)
pkt->get<uint64_t>());
break;
default:
pkt->result = Packet::BadAddress;
pkt->setBadAddress();
}
if (pkt->result == Packet::Unknown)
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
Tick
AlphaConsole::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;
@@ -245,7 +242,7 @@ AlphaConsole::write(PacketPtr pkt)
panic("Unknown 64bit access, %#x\n", daddr);
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

5
src/dev/alpha/tsunami_cchip.cc
View File

@@ -78,7 +78,6 @@ TsunamiCChip::read(PacketPtr pkt)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
@@ -181,7 +180,7 @@ TsunamiCChip::read(PacketPtr pkt)
DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
regnum, pkt->getSize(), pkt->get<uint64_t>());
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -365,7 +364,7 @@ TsunamiCChip::write(PacketPtr pkt)
panic("default in cchip read reached, accessing 0x%x\n");
} // swtich(regnum)
} // not BIG_TSUNAMI write
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

6
src/dev/alpha/tsunami_io.cc
View File

@@ -461,7 +461,6 @@ TsunamiIO::frequency() const
Tick
TsunamiIO::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;
@@ -520,14 +519,13 @@ TsunamiIO::read(PacketPtr pkt)
} else {
panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
Tick
TsunamiIO::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = pkt->getAddr() - pioAddr;
@@ -600,7 +598,7 @@ TsunamiIO::write(PacketPtr pkt)
panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

6
src/dev/alpha/tsunami_pchip.cc
View File

@@ -71,7 +71,6 @@ TsunamiPChip::TsunamiPChip(Params *p)
Tick
TsunamiPChip::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
pkt->allocate();
@@ -145,7 +144,7 @@ TsunamiPChip::read(PacketPtr pkt)
default:
panic("Default in PChip Read reached reading 0x%x\n", daddr);
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -153,7 +152,6 @@ TsunamiPChip::read(PacketPtr pkt)
Tick
TsunamiPChip::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
@@ -224,7 +222,7 @@ TsunamiPChip::write(PacketPtr pkt)
} // uint64_t
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

4
src/dev/i8254xGBe.cc
View File

@@ -271,7 +271,7 @@ IGbE::read(PacketPtr pkt)
pkt->set<uint32_t>(0);
};
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -543,7 +543,7 @@ IGbE::write(PacketPtr pkt)
panic("Write request to unknown register number: %#x\n", daddr);
};
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

14
src/dev/ide_ctrl.cc
View File

@@ -295,7 +295,7 @@ IdeController::readConfig(PacketPtr pkt)
default:
panic("invalid access size(?) for PCI configspace!\n");
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return configDelay;
}
@@ -403,7 +403,7 @@ IdeController::writeConfig(PacketPtr pkt)
bm_enabled = false;
break;
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return configDelay;
}
@@ -423,7 +423,7 @@ IdeController::read(PacketPtr pkt)
parseAddr(pkt->getAddr(), offset, channel, reg_type);
if (!io_enabled) {
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -490,7 +490,7 @@ IdeController::read(PacketPtr pkt)
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
offset, pkt->getSize(), pkt->get<uint32_t>());
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -506,7 +506,7 @@ IdeController::write(PacketPtr pkt)
parseAddr(pkt->getAddr(), offset, channel, reg_type);
if (!io_enabled) {
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
DPRINTF(IdeCtrl, "io not enabled\n");
return pioDelay;
}
@@ -514,7 +514,7 @@ IdeController::write(PacketPtr pkt)
switch (reg_type) {
case BMI_BLOCK:
if (!bm_enabled) {
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -673,7 +673,7 @@ IdeController::write(PacketPtr pkt)
offset, pkt->getSize(), pkt->get<uint32_t>());
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

4
src/dev/io_device.cc
View File

@@ -100,9 +100,7 @@ DmaPort::DmaPort(DmaDevice *dev, System *s)
bool
DmaPort::recvTiming(PacketPtr pkt)
{
if (pkt->result == Packet::Nacked) {
if (pkt->wasNacked()) {
DPRINTF(DMA, "Received nacked Pkt %#x with State: %#x Addr: %#x\n",
pkt, pkt->senderState, pkt->getAddr());

9
src/dev/isa_fake.cc
View File

@@ -56,7 +56,6 @@ IsaFake::IsaFake(Params *p)
Tick
IsaFake::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
if (params()->warnAccess != "")
warn("Device %s accessed by read to address %#x size=%d\n",
@@ -64,7 +63,7 @@ IsaFake::read(PacketPtr pkt)
if (params()->retBadAddr) {
DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
pkt->setBadAddress();
} else {
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@@ -85,7 +84,7 @@ IsaFake::read(PacketPtr pkt)
default:
panic("invalid access size!\n");
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
}
return pioDelay;
}
@@ -117,7 +116,7 @@ IsaFake::write(PacketPtr pkt)
if (params()->retBadAddr) {
DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->result = Packet::BadAddress;
pkt->setBadAddress();
} else {
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
@@ -140,7 +139,7 @@ IsaFake::write(PacketPtr pkt)
panic("invalid access size!\n");
}
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
}
return pioDelay;
}

8
src/dev/ns_gige.cc
View File

@@ -487,7 +487,7 @@ NSGigE::writeConfig(PacketPtr pkt)
ioEnable = false;
break;
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return configDelay;
}
@@ -519,7 +519,7 @@ NSGigE::read(PacketPtr pkt)
// doesn't actually DEPEND upon their values
// MIB are just hardware stats keepers
pkt->set<uint32_t>(0);
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
@@ -715,7 +715,7 @@ NSGigE::read(PacketPtr pkt)
DPRINTF(EthernetPIO, "read from %#x: data=%d data=%#x\n",
daddr, reg, reg);
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -1122,7 +1122,7 @@ NSGigE::write(PacketPtr pkt)
} else {
panic("Invalid Request Size");
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

4
src/dev/pciconfigall.cc
View File

@@ -54,7 +54,6 @@ PciConfigAll::PciConfigAll(Params *p)
Tick
PciConfigAll::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
pkt->allocate();
@@ -74,14 +73,13 @@ PciConfigAll::read(PacketPtr pkt)
default:
panic("invalid access size(?) for PCI configspace!\n");
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return params()->pio_delay;
}
Tick
PciConfigAll::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
panic("Attempting to write to config space on non-existant device\n");
M5_DUMMY_RETURN
}

5
src/dev/pcidev.cc
View File

@@ -68,7 +68,6 @@ PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
Tick
PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= configAddr &&
pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
@@ -156,7 +155,7 @@ PciDev::readConfig(PacketPtr pkt)
default:
panic("invalid access size(?) for PCI configspace!\n");
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return configDelay;
}
@@ -283,7 +282,7 @@ PciDev::writeConfig(PacketPtr pkt)
default:
panic("invalid access size(?) for PCI configspace!\n");
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return configDelay;
}

3
src/dev/sparc/dtod.cc
View File

@@ -74,7 +74,6 @@ DumbTOD::DumbTOD(Params *p)
Tick
DumbTOD::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
assert(pkt->getSize() == 8);
@@ -82,7 +81,7 @@ DumbTOD::read(PacketPtr pkt)
pkt->set(todTime);
todTime += 1000;
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

5
src/dev/sparc/iob.cc
View File

@@ -72,7 +72,6 @@ Iob::Iob(Params *p)
Tick
Iob::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
readIob(pkt);
@@ -81,7 +80,7 @@ Iob::read(PacketPtr pkt)
else
panic("Invalid address reached Iob\n");
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -176,7 +175,7 @@ Iob::write(PacketPtr pkt)
panic("Invalid address reached Iob\n");
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

6
src/dev/sparc/mm_disk.cc
View File

@@ -61,7 +61,6 @@ MmDisk::read(PacketPtr pkt)
uint32_t d32;
uint64_t d64;
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
accessAddr = pkt->getAddr() - pioAddr;
@@ -101,7 +100,7 @@ MmDisk::read(PacketPtr pkt)
panic("Invalid access size\n");
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -115,7 +114,6 @@ MmDisk::write(PacketPtr pkt)
uint32_t d32;
uint64_t d64;
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
accessAddr = pkt->getAddr() - pioAddr;
@@ -157,7 +155,7 @@ MmDisk::write(PacketPtr pkt)
panic("Invalid access size\n");
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}

6
src/dev/uart8250.cc
View File

@@ -111,7 +111,6 @@ Uart8250::Uart8250(Params *p)
Tick
Uart8250::read(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
assert(pkt->getSize() == 1);
@@ -186,7 +185,7 @@ Uart8250::read(PacketPtr pkt)
/* uint32_t d32 = *data;
DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
*/
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -194,7 +193,6 @@ Tick
Uart8250::write(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
assert(pkt->getSize() == 1);
@@ -272,7 +270,7 @@ Uart8250::write(PacketPtr pkt)
panic("Tried to access a UART port that doesn't exist\n");
break;
}
pkt->result = Packet::Success;
pkt->makeAtomicResponse();
return pioDelay;
}