arch-riscv: RISC-V HiFive Platform implementation

This patch implements the RISC-V HiFive Platform
(based on the SiFive HiFive series). The HiFive
platform requires a PLIC and CLINT device (based on
current HiFive boards).

The optional uart_int_id field redirects Console interrupts
to the PLIC interrupt controller.

PlicDevice is a wrapper around BasicPioDevice that
requires an interrupt ID. Interrupts are expected to
be raised via platform->postPciInterrupt(id).

VirtIOMMIO is a slight modification from the ARM
implementation such that interrupts are posted through
PLIC

PlicDevice is a wrapper around BasicPioDevice that
requires an interrupt ID. Interrupts are expected to
be raised via platform->postPciInterrupt(id).

VirtIOMMIO is a slight modification from the ARM
implementation such that interrupts are posted through
PLIC.

Uart8250 was modified slightly for easier Python
setup.

Change-Id: I4bbdb5f903b52a41d1b7e0ccc44877c46cd30d56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40599
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

src/dev/serial/Uart.py

@@ -60,3 +60,4 @@ class SimpleUart(Uart):
 class Uart8250(Uart):
     type = 'Uart8250'
     cxx_header = "dev/serial/uart8250.hh"
+    pio_size = Param.Addr(0x8, "Size of address range")

src/dev/serial/uart8250.cc

@@ -83,7 +83,8 @@ Uart8250::scheduleIntr(Event *event)
 
 
 Uart8250::Uart8250(const Params &p)
-    : Uart(p, 8), registers(this, name() + ".registers"), lastTxInt(0),
+    : Uart(p, p.pio_size), registers(this, name() + ".registers"),
+      lastTxInt(0),
       txIntrEvent([this]{ processIntrEvent(TX_INT); }, "TX"),
       rxIntrEvent([this]{ processIntrEvent(RX_INT); }, "RX")
 {