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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

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--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
This commit is contained in:
Ali Saidi
2007-03-07 15:04:31 -05:00
parent 329db76e47
commit 689cab36c9
68 changed files with 743 additions and 743 deletions
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18
src/cpu/checker/cpu.hh
View File

@@ -298,29 +298,29 @@ class CheckerCPU : public BaseCPU
thread->setNextPC(val);
}
MiscReg readMiscRegNoEffect(int misc_reg)
{
return thread->readMiscRegNoEffect(misc_reg);
}
MiscReg readMiscReg(int misc_reg)
{
return thread->readMiscReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg)
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
return thread->readMiscRegWithEffect(misc_reg);
result.integer = val;
miscRegIdxs.push(misc_reg);
return thread->setMiscRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val)
{
result.integer = val;
miscRegIdxs.push(misc_reg);
return thread->setMiscReg(misc_reg, val);
}
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
miscRegIdxs.push(misc_reg);
return thread->setMiscRegWithEffect(misc_reg, val);
}
void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
void recordNextPCChange(uint64_t val) { changedNextPC = true; }

10
src/cpu/checker/cpu_impl.hh
View File

@@ -386,13 +386,13 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
int misc_reg_idx = miscRegIdxs.front();
miscRegIdxs.pop();
if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
thread->readMiscReg(misc_reg_idx)) {
if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
thread->readMiscRegNoEffect(misc_reg_idx)) {
warn("%lli: Misc reg idx %i (side effect) does not match! "
"Inst: %#x, checker: %#x",
curTick, misc_reg_idx,
inst->tcBase()->readMiscReg(misc_reg_idx),
thread->readMiscReg(misc_reg_idx));
inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
thread->readMiscRegNoEffect(misc_reg_idx));
handleError(inst);
}
}
@@ -432,7 +432,7 @@ Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
} else if (idx < TheISA::Fpcr_DepTag) {
thread->setFloatRegBits(idx, inst->readIntResult());
} else {
thread->setMiscReg(idx, inst->readIntResult());
thread->setMiscRegNoEffect(idx, inst->readIntResult());
}
}

16
src/cpu/checker/thread_context.hh
View File

@@ -248,11 +248,17 @@ class CheckerThreadContext : public ThreadContext
checkerCPU->recordNextPCChange(val);
}
MiscReg readMiscRegNoEffect(int misc_reg)
{ return actualTC->readMiscRegNoEffect(misc_reg); }
MiscReg readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
MiscReg readMiscRegWithEffect(int misc_reg)
{ return actualTC->readMiscRegWithEffect(misc_reg); }
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
checkerTC->setMiscRegNoEffect(misc_reg, val);
actualTC->setMiscRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val)
{
@@ -260,12 +266,6 @@ class CheckerThreadContext : public ThreadContext
actualTC->setMiscReg(misc_reg, val);
}
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
checkerTC->setMiscRegWithEffect(misc_reg, val);
actualTC->setMiscRegWithEffect(misc_reg, val);
}
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }

8
src/cpu/exec_context.hh
View File

@@ -100,18 +100,18 @@ class ExecContext {
void setNextNPC(uint64_t val);
/** Reads a miscellaneous register. */
MiscReg readMiscReg(int misc_reg);
MiscReg readMiscRegNoEffect(int misc_reg);
/** Reads a miscellaneous register, handling any architectural
* side effects due to reading that register. */
MiscReg readMiscRegWithEffect(int misc_reg);
MiscReg readMiscReg(int misc_reg);
/** Sets a miscellaneous register. */
void setMiscReg(int misc_reg, const MiscReg &val);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
/** Sets a miscellaneous register, handling any architectural
* side effects due to writing that register. */
void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val);
/** Records the effective address of the instruction. Only valid
* for memory ops. */

98
src/cpu/exetrace.cc
View File

@@ -171,14 +171,14 @@ Trace::InstRecord::dump()
outs << "PC = " << thread->readNextPC();
outs << " NPC = " << thread->readNextNPC();
newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
//newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
//newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_CCR);
if(newVal != ccr)
{
outs << " CCR = " << newVal;
ccr = newVal;
}
newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1);
//newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
//newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_Y);
if(newVal != y)
{
outs << " Y = " << newVal;
@@ -387,30 +387,30 @@ Trace::InstRecord::dump()
diffFpRegs = true;
}
}
uint64_t oldTl = thread->readMiscReg(MISCREG_TL);
uint64_t oldTl = thread->readMiscRegNoEffect(MISCREG_TL);
if (oldTl != shared_data->tl)
diffTl = true;
for (int i = 1; i <= MaxTL; i++) {
thread->setMiscReg(MISCREG_TL, i);
if (thread->readMiscReg(MISCREG_TPC) !=
thread->setMiscRegNoEffect(MISCREG_TL, i);
if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
shared_data->tpc[i-1])
diffTpc = true;
if (thread->readMiscReg(MISCREG_TNPC) !=
if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
shared_data->tnpc[i-1])
diffTnpc = true;
if (thread->readMiscReg(MISCREG_TSTATE) !=
if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
shared_data->tstate[i-1])
diffTstate = true;
if (thread->readMiscReg(MISCREG_TT) !=
if (thread->readMiscRegNoEffect(MISCREG_TT) !=
shared_data->tt[i-1])
diffTt = true;
if (thread->readMiscReg(MISCREG_HTSTATE) !=
if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
shared_data->htstate[i-1])
diffHtstate = true;
}
thread->setMiscReg(MISCREG_TL, oldTl);
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
if(shared_data->tba != thread->readMiscReg(MISCREG_TBA))
if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
diffTba = true;
//When the hpstate register is read by an instruction,
//legion has bit 11 set. When it's in storage, it doesn't.
@@ -418,50 +418,50 @@ Trace::InstRecord::dump()
//of the registers like that, the bit is always set to 1 and
//we just don't compare it. It's not supposed to matter
//anyway.
if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE))
if((shared_data->hpstate | (1 << 11)) != thread->readMiscRegNoEffect(MISCREG_HPSTATE))
diffHpstate = true;
if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA))
if(shared_data->htba != thread->readMiscRegNoEffect(MISCREG_HTBA))
diffHtba = true;
if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE))
if(shared_data->pstate != thread->readMiscRegNoEffect(MISCREG_PSTATE))
diffPstate = true;
//if(shared_data->y != thread->readMiscReg(MISCREG_Y))
//if(shared_data->y != thread->readMiscRegNoEffect(MISCREG_Y))
if(shared_data->y !=
thread->readIntReg(NumIntArchRegs + 1))
diffY = true;
if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) {
if(shared_data->fsr != thread->readMiscRegNoEffect(MISCREG_FSR)) {
diffFsr = true;
if (mbits(shared_data->fsr, 63,10) ==
mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) {
thread->setMiscReg(MISCREG_FSR, shared_data->fsr);
mbits(thread->readMiscRegNoEffect(MISCREG_FSR), 63,10)) {
thread->setMiscRegNoEffect(MISCREG_FSR, shared_data->fsr);
diffFsr = false;
}
}
//if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
//if(shared_data->ccr != thread->readMiscRegNoEffect(MISCREG_CCR))
if(shared_data->ccr !=
thread->readIntReg(NumIntArchRegs + 2))
diffCcr = true;
if(shared_data->gl != thread->readMiscReg(MISCREG_GL))
if(shared_data->gl != thread->readMiscRegNoEffect(MISCREG_GL))
diffGl = true;
if(shared_data->asi != thread->readMiscReg(MISCREG_ASI))
if(shared_data->asi != thread->readMiscRegNoEffect(MISCREG_ASI))
diffAsi = true;
if(shared_data->pil != thread->readMiscReg(MISCREG_PIL))
if(shared_data->pil != thread->readMiscRegNoEffect(MISCREG_PIL))
diffPil = true;
if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
if(shared_data->cwp != thread->readMiscRegNoEffect(MISCREG_CWP))
diffCwp = true;
//if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
//if(shared_data->cansave != thread->readMiscRegNoEffect(MISCREG_CANSAVE))
if(shared_data->cansave !=
thread->readIntReg(NumIntArchRegs + 3))
diffCansave = true;
//if(shared_data->canrestore !=
// thread->readMiscReg(MISCREG_CANRESTORE))
// thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
if(shared_data->canrestore !=
thread->readIntReg(NumIntArchRegs + 4))
diffCanrestore = true;
//if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
//if(shared_data->otherwin != thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
if(shared_data->otherwin !=
thread->readIntReg(NumIntArchRegs + 6))
diffOtherwin = true;
//if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
//if(shared_data->cleanwin != thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
if(shared_data->cleanwin !=
thread->readIntReg(NumIntArchRegs + 5))
diffCleanwin = true;
@@ -569,78 +569,78 @@ Trace::InstRecord::dump()
printSectionHeader(outs, "General State");
printColumnLabels(outs);
printRegPair(outs, "HPstate",
thread->readMiscReg(MISCREG_HPSTATE),
thread->readMiscRegNoEffect(MISCREG_HPSTATE),
shared_data->hpstate | (1 << 11));
printRegPair(outs, "Htba",
thread->readMiscReg(MISCREG_HTBA),
thread->readMiscRegNoEffect(MISCREG_HTBA),
shared_data->htba);
printRegPair(outs, "Pstate",
thread->readMiscReg(MISCREG_PSTATE),
thread->readMiscRegNoEffect(MISCREG_PSTATE),
shared_data->pstate);
printRegPair(outs, "Y",
//thread->readMiscReg(MISCREG_Y),
//thread->readMiscRegNoEffect(MISCREG_Y),
thread->readIntReg(NumIntArchRegs + 1),
shared_data->y);
printRegPair(outs, "FSR",
thread->readMiscReg(MISCREG_FSR),
thread->readMiscRegNoEffect(MISCREG_FSR),
shared_data->fsr);
printRegPair(outs, "Ccr",
//thread->readMiscReg(MISCREG_CCR),
//thread->readMiscRegNoEffect(MISCREG_CCR),
thread->readIntReg(NumIntArchRegs + 2),
shared_data->ccr);
printRegPair(outs, "Tl",
thread->readMiscReg(MISCREG_TL),
thread->readMiscRegNoEffect(MISCREG_TL),
shared_data->tl);
printRegPair(outs, "Gl",
thread->readMiscReg(MISCREG_GL),
thread->readMiscRegNoEffect(MISCREG_GL),
shared_data->gl);
printRegPair(outs, "Asi",
thread->readMiscReg(MISCREG_ASI),
thread->readMiscRegNoEffect(MISCREG_ASI),
shared_data->asi);
printRegPair(outs, "Pil",
thread->readMiscReg(MISCREG_PIL),
thread->readMiscRegNoEffect(MISCREG_PIL),
shared_data->pil);
printRegPair(outs, "Cwp",
thread->readMiscReg(MISCREG_CWP),
thread->readMiscRegNoEffect(MISCREG_CWP),
shared_data->cwp);
printRegPair(outs, "Cansave",
//thread->readMiscReg(MISCREG_CANSAVE),
//thread->readMiscRegNoEffect(MISCREG_CANSAVE),
thread->readIntReg(NumIntArchRegs + 3),
shared_data->cansave);
printRegPair(outs, "Canrestore",
//thread->readMiscReg(MISCREG_CANRESTORE),
//thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
thread->readIntReg(NumIntArchRegs + 4),
shared_data->canrestore);
printRegPair(outs, "Otherwin",
//thread->readMiscReg(MISCREG_OTHERWIN),
//thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
thread->readIntReg(NumIntArchRegs + 6),
shared_data->otherwin);
printRegPair(outs, "Cleanwin",
//thread->readMiscReg(MISCREG_CLEANWIN),
//thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
thread->readIntReg(NumIntArchRegs + 5),
shared_data->cleanwin);
outs << endl;
for (int i = 1; i <= MaxTL; i++) {
printLevelHeader(outs, i);
printColumnLabels(outs);
thread->setMiscReg(MISCREG_TL, i);
thread->setMiscRegNoEffect(MISCREG_TL, i);
printRegPair(outs, "Tpc",
thread->readMiscReg(MISCREG_TPC),
thread->readMiscRegNoEffect(MISCREG_TPC),
shared_data->tpc[i-1]);
printRegPair(outs, "Tnpc",
thread->readMiscReg(MISCREG_TNPC),
thread->readMiscRegNoEffect(MISCREG_TNPC),
shared_data->tnpc[i-1]);
printRegPair(outs, "Tstate",
thread->readMiscReg(MISCREG_TSTATE),
thread->readMiscRegNoEffect(MISCREG_TSTATE),
shared_data->tstate[i-1]);
printRegPair(outs, "Tt",
thread->readMiscReg(MISCREG_TT),
thread->readMiscRegNoEffect(MISCREG_TT),
shared_data->tt[i-1]);
printRegPair(outs, "Htstate",
thread->readMiscReg(MISCREG_HTSTATE),
thread->readMiscRegNoEffect(MISCREG_HTSTATE),
shared_data->htstate[i-1]);
}
thread->setMiscReg(MISCREG_TL, oldTl);
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
outs << endl;
printSectionHeader(outs, "General Purpose Registers");

8
src/cpu/o3/alpha/cpu.hh
View File

@@ -106,21 +106,21 @@ class AlphaO3CPU : public FullO3CPU<Impl>
#endif
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
/** Sets a miscellaneous register. */
void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
unsigned tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
unsigned tid);
/** Initiates a squash of all in-flight instructions for a given

24
src/cpu/o3/alpha/cpu_impl.hh
View File

@@ -152,6 +152,13 @@ AlphaO3CPU<Impl>::regStats()
}
template <class Impl>
TheISA::MiscReg
AlphaO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
{
return this->regFile.readMiscRegNoEffect(misc_reg, tid);
}
template <class Impl>
TheISA::MiscReg
AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
@@ -159,27 +166,20 @@ AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
return this->regFile.readMiscReg(misc_reg, tid);
}
template <class Impl>
TheISA::MiscReg
AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
{
return this->regFile.readMiscRegWithEffect(misc_reg, tid);
}
template <class Impl>
void
AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val,
AlphaO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
unsigned tid)
{
this->regFile.setMiscReg(misc_reg, val, tid);
this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
}
template <class Impl>
void
AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
AlphaO3CPU<Impl>::setMiscReg(int misc_reg,
const TheISA::MiscReg &val, unsigned tid)
{
this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
this->regFile.setMiscReg(misc_reg, val, tid);
}
template <class Impl>
@@ -209,7 +209,7 @@ Fault
AlphaO3CPU<Impl>::hwrei(unsigned tid)
{
// Need to clear the lock flag upon returning from an interrupt.
this->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, false, tid);
this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
this->thread[tid]->kernelStats->hwrei();

24
src/cpu/o3/alpha/dyn_inst.hh
View File

@@ -95,39 +95,39 @@ class AlphaDynInst : public BaseDynInst<Impl>
public:
/** Reads a miscellaneous register. */
MiscReg readMiscReg(int misc_reg)
MiscReg readMiscRegNoEffect(int misc_reg)
{
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
}
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
MiscReg readMiscRegWithEffect(int misc_reg)
MiscReg readMiscReg(int misc_reg)
{
return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
/** Sets a misc. register. */
void setMiscReg(int misc_reg, const MiscReg &val)
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
}
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
return this->cpu->setMiscRegWithEffect(misc_reg, val,
return this->cpu->setMiscReg(misc_reg, val,
this->threadNumber);
}
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readMiscReg(
return this->cpu->readMiscRegNoEffect(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
this->threadNumber);
}
@@ -137,7 +137,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
*/
TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
{
return this->cpu->readMiscRegWithEffect(
return this->cpu->readMiscReg(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
this->threadNumber);
}
@@ -146,7 +146,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscReg(
return this->cpu->setMiscRegNoEffect(
si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
val, this->threadNumber);
}
@@ -157,7 +157,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setMiscRegOperandWithEffect(const StaticInst *si, int idx,
const MiscReg &val)
{
return this->cpu->setMiscRegWithEffect(
return this->cpu->setMiscReg(
si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
val, this->threadNumber);
}

2
src/cpu/o3/alpha/dyn_inst_impl.hh
View File

@@ -118,7 +118,7 @@ AlphaDynInst<Impl>::hwrei()
return new AlphaISA::UnimplementedOpcodeFault;
// Set the next PC based on the value of the EXC_ADDR IPR.
this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
this->threadNumber));
// Tell CPU to clear any state it needs to if a hwrei is taken.

8
src/cpu/o3/mips/cpu.hh
View File

@@ -87,20 +87,20 @@ class MipsO3CPU : public FullO3CPU<Impl>
}
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
/** Sets a miscellaneous register. */
void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscRegWithEffect(int misc_reg,
void setMiscReg(int misc_reg,
const TheISA::MiscReg &val, unsigned tid);
/** Initiates a squash of all in-flight instructions for a given

24
src/cpu/o3/mips/cpu_impl.hh
View File

@@ -133,6 +133,13 @@ MipsO3CPU<Impl>::regStats()
}
template <class Impl>
MiscReg
MipsO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
{
return this->regFile.readMiscRegNoEffect(misc_reg, tid);
}
template <class Impl>
MiscReg
MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
@@ -141,25 +148,18 @@ MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
}
template <class Impl>
MiscReg
MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
void
MipsO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
{
return this->regFile.readMiscRegWithEffect(misc_reg, tid);
this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
}
template <class Impl>
void
MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
{
this->regFile.setMiscReg(misc_reg, val, tid);
}
template <class Impl>
void
MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val,
unsigned tid)
{
this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
this->regFile.setMiscReg(misc_reg, val, tid);
}
template <class Impl>

16
src/cpu/o3/mips/dyn_inst.hh
View File

@@ -93,32 +93,32 @@ class MipsDynInst : public BaseDynInst<Impl>
public:
/** Reads a miscellaneous register. */
MiscReg readMiscReg(int misc_reg)
MiscReg readMiscRegNoEffect(int misc_reg)
{
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
}
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
MiscReg readMiscRegWithEffect(int misc_reg)
MiscReg readMiscReg(int misc_reg)
{
return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
/** Sets a misc. register. */
void setMiscReg(int misc_reg, const MiscReg &val)
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
this->instResult.integer = val;
this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
}
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
void setMiscReg(int misc_reg, const MiscReg &val)
{
return this->cpu->setMiscRegWithEffect(misc_reg, val,
return this->cpu->setMiscReg(misc_reg, val,
this->threadNumber);
}

16
src/cpu/o3/regfile.hh
View File

@@ -225,26 +225,26 @@ class PhysRegFile
floatRegFile[reg_idx].q = val;
}
MiscReg readMiscReg(int misc_reg, unsigned thread_id)
MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id)
{
return miscRegs[thread_id].readReg(misc_reg);
return miscRegs[thread_id].readRegNoEffect(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
MiscReg readMiscReg(int misc_reg, unsigned thread_id)
{
return miscRegs[thread_id].readRegWithEffect(misc_reg,
return miscRegs[thread_id].readReg(misc_reg,
cpu->tcBase(thread_id));
}
void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned thread_id)
{
miscRegs[thread_id].setReg(misc_reg, val);
miscRegs[thread_id].setRegNoEffect(misc_reg, val);
}
void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
void setMiscReg(int misc_reg, const MiscReg &val,
unsigned thread_id)
{
miscRegs[thread_id].setRegWithEffect(misc_reg, val,
miscRegs[thread_id].setReg(misc_reg, val,
cpu->tcBase(thread_id));
}

8
src/cpu/o3/sparc/cpu.hh
View File

@@ -106,20 +106,20 @@ class SparcO3CPU : public FullO3CPU<Impl>
#endif
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
/** Sets a miscellaneous register. */
void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
unsigned tid);
/** Initiates a squash of all in-flight instructions for a given

22
src/cpu/o3/sparc/cpu_impl.hh
View File

@@ -151,6 +151,13 @@ SparcO3CPU<Impl>::regStats()
}
template <class Impl>
TheISA::MiscReg
SparcO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
{
return this->regFile.readMiscRegNoEffect(misc_reg, tid);
}
template <class Impl>
TheISA::MiscReg
SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
@@ -159,10 +166,11 @@ SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
}
template <class Impl>
TheISA::MiscReg
SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
void
SparcO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
const SparcISA::MiscReg &val, unsigned tid)
{
return this->regFile.readMiscRegWithEffect(misc_reg, tid);
this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
}
template <class Impl>
@@ -173,14 +181,6 @@ SparcO3CPU<Impl>::setMiscReg(int misc_reg,
this->regFile.setMiscReg(misc_reg, val, tid);
}
template <class Impl>
void
SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
const SparcISA::MiscReg &val, unsigned tid)
{
this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
}
template <class Impl>
void
SparcO3CPU<Impl>::squashFromTC(unsigned tid)

24
src/cpu/o3/sparc/dyn_inst.hh
View File

@@ -77,39 +77,39 @@ class SparcDynInst : public BaseDynInst<Impl>
public:
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscReg(int misc_reg)
TheISA::MiscReg readMiscRegNoEffect(int misc_reg)
{
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
}
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
TheISA::MiscReg readMiscRegWithEffect(int misc_reg)
TheISA::MiscReg readMiscReg(int misc_reg)
{
return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
/** Sets a misc. register. */
void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber);
}
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val)
void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
{
return this->cpu->setMiscRegWithEffect(misc_reg, val,
return this->cpu->setMiscReg(misc_reg, val,
this->threadNumber);
}
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readMiscReg(
return this->cpu->readMiscRegNoEffect(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
this->threadNumber);
}
@@ -119,7 +119,7 @@ class SparcDynInst : public BaseDynInst<Impl>
*/
TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
{
return this->cpu->readMiscRegWithEffect(
return this->cpu->readMiscReg(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
this->threadNumber);
}
@@ -129,7 +129,7 @@ class SparcDynInst : public BaseDynInst<Impl>
int idx, const TheISA::MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscReg(
return this->cpu->setMiscRegNoEffect(
si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
val, this->threadNumber);
}
@@ -140,7 +140,7 @@ class SparcDynInst : public BaseDynInst<Impl>
void setMiscRegOperandWithEffect(
const StaticInst *si, int idx, const TheISA::MiscReg &val)
{
return this->cpu->setMiscRegWithEffect(
return this->cpu->setMiscReg(
si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
val, this->threadNumber);
}

12
src/cpu/o3/thread_context.hh
View File

@@ -206,20 +206,20 @@ class O3ThreadContext : public ThreadContext
virtual void setNextPC(uint64_t val);
/** Reads a miscellaneous register. */
virtual MiscReg readMiscReg(int misc_reg)
{ return cpu->readMiscReg(misc_reg, thread->readTid()); }
virtual MiscReg readMiscRegNoEffect(int misc_reg)
{ return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
/** Reads a misc. register, including any side-effects the
* read might have as defined by the architecture. */
virtual MiscReg readMiscRegWithEffect(int misc_reg)
{ return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); }
virtual MiscReg readMiscReg(int misc_reg)
{ return cpu->readMiscReg(misc_reg, thread->readTid()); }
/** Sets a misc. register. */
virtual void setMiscReg(int misc_reg, const MiscReg &val);
virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
/** Sets a misc. register, including any side-effects the
* write might have as defined by the architecture. */
virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
virtual void setMiscReg(int misc_reg, const MiscReg &val);
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.

8
src/cpu/o3/thread_context_impl.hh
View File

@@ -442,9 +442,9 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val)
template <class Impl>
void
O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
cpu->setMiscReg(misc_reg, val, thread->readTid());
cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
@@ -454,10 +454,10 @@ O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
O3ThreadContext<Impl>::setMiscReg(int misc_reg,
const MiscReg &val)
{
cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid());
cpu->setMiscReg(misc_reg, val, thread->readTid());
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {

6
src/cpu/ozone/cpu.hh
View File

@@ -235,14 +235,14 @@ class OzoneCPU : public BaseCPU
public:
// ISA stuff:
MiscReg readMiscRegNoEffect(int misc_reg);
MiscReg readMiscReg(int misc_reg);
MiscReg readMiscRegWithEffect(int misc_reg);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val);
void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
unsigned readStCondFailures()
{ return thread->storeCondFailures; }

34
src/cpu/ozone/cpu_impl.hh
View File

@@ -1089,16 +1089,28 @@ OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
template <class Impl>
TheISA::MiscReg
OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
OzoneCPU<Impl>::OzoneTC::readMiscRegNoEffect(int misc_reg)
{
return thread->miscRegFile.readReg(misc_reg);
return thread->miscRegFile.readRegNoEffect(misc_reg);
}
template <class Impl>
TheISA::MiscReg
OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg)
OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
{
return thread->miscRegFile.readRegWithEffect(misc_reg, this);
return thread->miscRegFile.readReg(misc_reg, this);
}
template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
thread->miscRegFile.setRegNoEffect(misc_reg, val);
if (!thread->inSyscall) {
cpu->squashFromTC();
}
}
template <class Impl>
@@ -1106,19 +1118,7 @@ void
OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
thread->miscRegFile.setReg(misc_reg, val);
if (!thread->inSyscall) {
cpu->squashFromTC();
}
}
template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
thread->miscRegFile.setRegWithEffect(misc_reg, val, this);
thread->miscRegFile.setReg(misc_reg, val, this);
if (!thread->inSyscall) {
cpu->squashFromTC();

6
src/cpu/ozone/dyn_inst.hh
View File

@@ -231,14 +231,14 @@ class OzoneDynInst : public BaseDynInst<Impl>
public:
// ISA stuff
MiscReg readMiscRegNoEffect(int misc_reg);
MiscReg readMiscReg(int misc_reg);
MiscReg readMiscRegWithEffect(int misc_reg);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val);
void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
#if FULL_SYSTEM
Fault hwrei();
void trap(Fault fault);

24
src/cpu/ozone/dyn_inst_impl.hh
View File

@@ -217,6 +217,13 @@ OzoneDynInst<Impl>::clearMemDependents()
memDependents.clear();
}
template <class Impl>
TheISA::MiscReg
OzoneDynInst<Impl>::readMiscRegNoEffect(int misc_reg)
{
return this->thread->readMiscRegNoEffect(misc_reg);
}
template <class Impl>
TheISA::MiscReg
OzoneDynInst<Impl>::readMiscReg(int misc_reg)
@@ -225,27 +232,20 @@ OzoneDynInst<Impl>::readMiscReg(int misc_reg)
}
template <class Impl>
TheISA::MiscReg
OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg)
void
OzoneDynInst<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
return this->thread->readMiscRegWithEffect(misc_reg);
this->setIntResult(val);
this->thread->setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
void
OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
{
this->setIntResult(val);
this->thread->setMiscReg(misc_reg, val);
}
template <class Impl>
void
OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
this->thread->setMiscRegWithEffect(misc_reg, val);
}
#if FULL_SYSTEM
template <class Impl>
@@ -255,7 +255,7 @@ OzoneDynInst<Impl>::hwrei()
if (!(this->readPC() & 0x3))
return new AlphaISA::UnimplementedOpcodeFault;
this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
this->cpu->hwrei();

14
src/cpu/ozone/inorder_back_end_impl.hh
View File

@@ -89,13 +89,13 @@ InorderBackEnd<Impl>::checkInterrupts()
int summary = 0;
if (thread->readMiscReg(IPR_ASTRR))
if (thread->readMiscRegNoEffect(IPR_ASTRR))
panic("asynchronous traps not implemented\n");
if (thread->readMiscReg(IPR_SIRR)) {
if (thread->readMiscRegNoEffect(IPR_SIRR)) {
for (int i = INTLEVEL_SOFTWARE_MIN;
i < INTLEVEL_SOFTWARE_MAX; i++) {
if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
if (thread->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
// See table 4-19 of the 21164 hardware reference
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
@@ -116,14 +116,14 @@ InorderBackEnd<Impl>::checkInterrupts()
}
}
if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
if (ipl && ipl > thread->readMiscRegNoEffect(IPR_IPLR)) {
thread->inSyscall = true;
thread->setMiscReg(IPR_ISR, summary);
thread->setMiscReg(IPR_INTID, ipl);
thread->setMiscRegNoEffect(IPR_ISR, summary);
thread->setMiscRegNoEffect(IPR_INTID, ipl);
Fault(new InterruptFault)->invoke(xc);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
thread->readMiscReg(IPR_IPLR), ipl, summary);
thread->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
// May need to go 1 inst prior
squashPending = true;

2
src/cpu/ozone/lw_back_end_impl.hh
View File

@@ -1193,7 +1193,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
#if FULL_SYSTEM
if (thread->profile) {
// bool usermode =
// (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
// (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
// thread->profilePC = usermode ? 1 : inst->readPC();
thread->profilePC = inst->readPC();
ProfileNode *node = thread->profile->consume(thread->getTC(),

20
src/cpu/ozone/thread_state.hh
View File

@@ -115,24 +115,24 @@ struct OzoneThreadState : public ThreadState {
ThreadContext *getTC() { return tc; }
MiscReg readMiscReg(int misc_reg)
MiscReg readMiscRegNoEffect(int misc_reg)
{
return miscRegFile.readReg(misc_reg);
return miscRegFile.readRegNoEffect(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg)
MiscReg readMiscReg(int misc_reg)
{
return miscRegFile.readRegWithEffect(misc_reg, tc);
return miscRegFile.readReg(misc_reg, tc);
}
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
miscRegFile.setRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val)
{
miscRegFile.setReg(misc_reg, val);
}
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
miscRegFile.setRegWithEffect(misc_reg, val, tc);
miscRegFile.setReg(misc_reg, val, tc);
}
uint64_t readPC()

22
src/cpu/simple/base.hh
View File

@@ -284,14 +284,19 @@ class BaseSimpleCPU : public BaseCPU
void setNextPC(uint64_t val) { thread->setNextPC(val); }
void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
MiscReg readMiscRegNoEffect(int misc_reg)
{
return thread->readMiscRegNoEffect(misc_reg);
}
MiscReg readMiscReg(int misc_reg)
{
return thread->readMiscReg(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg)
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
return thread->readMiscRegWithEffect(misc_reg);
return thread->setMiscRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val)
@@ -299,34 +304,29 @@ class BaseSimpleCPU : public BaseCPU
return thread->setMiscReg(misc_reg, val);
}
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return thread->setMiscRegWithEffect(misc_reg, val);
}
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscReg(reg_idx);
return thread->readMiscRegNoEffect(reg_idx);
}
MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscRegWithEffect(reg_idx);
return thread->readMiscReg(reg_idx);
}
void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscReg(reg_idx, val);
return thread->setMiscRegNoEffect(reg_idx, val);
}
void setMiscRegOperandWithEffect(
const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscRegWithEffect(reg_idx, val);
return thread->setMiscReg(reg_idx, val);
}
unsigned readStCondFailures() {

20
src/cpu/simple_thread.hh
View File

@@ -350,24 +350,24 @@ class SimpleThread : public ThreadState
regs.setNextNPC(val);
}
MiscReg readMiscReg(int misc_reg)
MiscReg readMiscRegNoEffect(int misc_reg)
{
return regs.readMiscReg(misc_reg);
return regs.readMiscRegNoEffect(misc_reg);
}
MiscReg readMiscRegWithEffect(int misc_reg)
MiscReg readMiscReg(int misc_reg)
{
return regs.readMiscRegWithEffect(misc_reg, tc);
return regs.readMiscReg(misc_reg, tc);
}
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
return regs.setMiscRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val)
{
return regs.setMiscReg(misc_reg, val);
}
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
return regs.setMiscRegWithEffect(misc_reg, val, tc);
return regs.setMiscReg(misc_reg, val, tc);
}
unsigned readStCondFailures() { return storeCondFailures; }

16
src/cpu/thread_context.hh
View File

@@ -226,14 +226,14 @@ class ThreadContext
virtual void setNextNPC(uint64_t val) = 0;
virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
virtual MiscReg readMiscReg(int misc_reg) = 0;
virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0;
virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
virtual unsigned readStCondFailures() = 0;
@@ -412,18 +412,18 @@ class ProxyThreadContext : public ThreadContext
void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
MiscReg readMiscRegNoEffect(int misc_reg)
{ return actualTC->readMiscRegNoEffect(misc_reg); }
MiscReg readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
MiscReg readMiscRegWithEffect(int misc_reg)
{ return actualTC->readMiscRegWithEffect(misc_reg); }
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscRegNoEffect(misc_reg, val); }
void setMiscReg(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscReg(misc_reg, val); }
void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscRegWithEffect(misc_reg, val); }
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }