From 688f8fb03b2bf62234611b0e5f36a02d8f268497 Mon Sep 17 00:00:00 2001
From: Robert Hauser <85344819+robhau@users.noreply.github.com>
Date: Tue, 21 May 2024 18:59:25 +0200
Subject: [PATCH] arch-riscv: add exception code to DPRINTFS msg (#1153)

Change-Id: Ib5d1dc991f18256ec634c604c776629ea31317a9
---
 src/arch/riscv/faults.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 634171fc5c..5d82750914 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -61,8 +61,8 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 {
     auto pc_state = tc->pcState().as<PCState>();
 
-    DPRINTFS(Faults, tc->getCpuPtr(), "Fault (%s) at PC: %s\n",
-             name(), pc_state);
+    DPRINTFS(Faults, tc->getCpuPtr(), "Fault (%s, %u) at PC: %s\n",
+             name(), exception(), pc_state);
 
     if (FullSystem) {
         PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);