From 6841e1aa5a1738961940fece2b35baf77c8c224d Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Fri, 10 Mar 2023 13:53:08 -0800 Subject: [PATCH] stdlib: Fix bug in MESI_Three_Level_Cache initialization Change-Id: I2d06c842955aa1868053a0d852fc523392480154 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68857 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- .../cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py | 4 ++-- .../cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py index 9f47e411f8..b4854816fb 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py @@ -68,14 +68,14 @@ class L1Cache(L0Cache_Controller): self.Icache = RubyCache( size=l1i_size, assoc=l1i_assoc, - start_index_bit=self.getBlockSizeBits(cache_line_size.value), + start_index_bit=self.getBlockSizeBits(cache_line_size), is_icache=True, replacement_policy=LRURP(), ) self.Dcache = RubyCache( size=l1d_size, assoc=l1d_assoc, - start_index_bit=self.getBlockSizeBits(cache_line_size.value), + start_index_bit=self.getBlockSizeBits(cache_line_size), is_icache=False, replacement_policy=LRURP(), ) diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py index d8c965924e..d54e1ab8dc 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py @@ -67,7 +67,7 @@ class L2Cache(L1Cache_Controller): self.cache = RubyCache( size=l2_size, assoc=l2_assoc, - start_index_bit=self.getBlockSizeBits(cache_line_size.value), + start_index_bit=self.getBlockSizeBits(cache_line_size), is_icache=False, ) # l2_select_num_bits is ruby backend terminology.