diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py
index ca533bef0e..bce7f2497f 100644
--- a/src/arch/riscv/RiscvISA.py
+++ b/src/arch/riscv/RiscvISA.py
@@ -96,6 +96,9 @@ class RiscvISA(BaseISA):
         ELEN in Ch. 2 of RISC-V vector spec",
     )
 
+    enable_Zicbom_fs = Param.Bool(True, "Enable Zicbom extension in FS mode")
+    enable_Zicboz_fs = Param.Bool(True, "Enable Zicboz extension in FS mode")
+
     def get_isa_string(self):
         isa_extensions = []
         # check for the base ISA type
@@ -110,8 +113,10 @@ class RiscvISA(BaseISA):
             isa_extensions.append("v")
         isa_string = "".join(isa_extensions)
 
-        isa_string += "_Zicbom"  # Cache-block Management Instructions
-        isa_string += "_Zicboz"  # Cache-block Zero Instruction
+        if self.enable_Zicbom_fs.value:
+            isa_string += "_Zicbom"  # Cache-block Management Instructions
+        if self.enable_Zicboz_fs.value:
+            isa_string += "_Zicboz"  # Cache-block Zero Instruction
         isa_string += "_Zicntr"  # Performance Couter Spec
         isa_string += "_Zicsr"  # RMW CSR Instructions (Privileged Spec)
         isa_string += "_Zifencei"  # FENCE.I Instruction (Unprivileged Spec)
diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py
index 9b0d6454e1..5e5af815a4 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -279,6 +279,18 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
             node.append(FdtPropertyStrings("device_type", "cpu"))
             node.append(FdtPropertyWords("reg", state.CPUAddrCells(i)))
             node.append(FdtPropertyStrings("mmu-type", "riscv,sv48"))
+            if core.core.isa[0].enable_Zicbom_fs.value:
+                node.append(
+                    FdtPropertyWords(
+                        "riscv,cbom-block-size", self.get_cache_line_size()
+                    )
+                )
+            if core.core.isa[0].enable_Zicboz_fs.value:
+                node.append(
+                    FdtPropertyWords(
+                        "riscv,cboz-block-size", self.get_cache_line_size()
+                    )
+                )
             node.append(FdtPropertyStrings("status", "okay"))
             node.append(
                 FdtPropertyStrings(