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misc: Merge branch 'release-staging-v21-0' into develop

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Change-Id: I0ad043ded56fb848e045057a1e7a56ea39797906
This commit is contained in:
Bobby R. Bruce
2021-03-18 11:13:14 -07:00
parent 6a7403f1a2 377a96644e
commit 68064d8043
49 changed files with 9819 additions and 226 deletions
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2
src/arch/generic/mmu.hh
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@@ -103,7 +103,7 @@ class BaseMMU : public SimObject
return getTlb(mode)->finalizePhysical(req, tc, mode);
}
void takeOverFrom(BaseMMU *old_mmu);
virtual void takeOverFrom(BaseMMU *old_mmu);
public:
BaseTLB* dtb;

4
src/arch/riscv/RiscvMMU.py
View File

@@ -35,6 +35,8 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
from m5.objects.BaseMMU import BaseMMU
from m5.objects.RiscvTLB import RiscvTLB
from m5.objects.PMAChecker import PMAChecker
@@ -45,7 +47,7 @@ class RiscvMMU(BaseMMU):
cxx_header = 'arch/riscv/mmu.hh'
itb = RiscvTLB()
dtb = RiscvTLB()
pma_checker = PMAChecker()
pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
@classmethod
def walkerPorts(cls):

4
src/arch/riscv/RiscvTLB.py
View File

@@ -43,7 +43,7 @@ class RiscvPagetableWalker(ClockedObject):
num_squash_per_cycle = Param.Unsigned(4,
"Number of outstanding walks that can be squashed per cycle")
# Grab the pma_checker from the MMU
pma_checker = Param.PMAChecker(Parent.any, "PMA Chekcer")
pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
class RiscvTLB(BaseTLB):
type = 'RiscvTLB'
@@ -53,4 +53,4 @@ class RiscvTLB(BaseTLB):
walker = Param.RiscvPagetableWalker(\
RiscvPagetableWalker(), "page table walker")
# Grab the pma_checker from the MMU
pma_checker = Param.PMAChecker(Parent.any, "PMA Chekcer")
pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")

13
src/arch/riscv/mmu.hh
View File

@@ -40,6 +40,7 @@
#include "arch/generic/mmu.hh"
#include "arch/riscv/isa.hh"
#include "arch/riscv/pma_checker.hh"
#include "arch/riscv/tlb.hh"
#include "params/RiscvMMU.hh"
@@ -49,8 +50,10 @@ namespace RiscvISA {
class MMU : public BaseMMU
{
public:
PMAChecker *pma;
MMU(const RiscvMMUParams &p)
: BaseMMU(p)
: BaseMMU(p), pma(p.pma_checker)
{}
PrivilegeMode
@@ -64,6 +67,14 @@ class MMU : public BaseMMU
{
return static_cast<TLB*>(dtb)->getWalker();
}
void
takeOverFrom(BaseMMU *old_mmu) override
{
MMU *ommu = dynamic_cast<MMU*>(old_mmu);
BaseMMU::takeOverFrom(ommu);
pma->takeOverFrom(ommu->pma);
}
};
} // namespace RiscvISA

6
src/arch/riscv/pma_checker.cc
View File

@@ -81,3 +81,9 @@ PMAChecker::isUncacheable(PacketPtr pkt)
{
return isUncacheable(pkt->getAddrRange());
}
void
PMAChecker::takeOverFrom(PMAChecker *old)
{
uncacheable = old->uncacheable;
}

2
src/arch/riscv/pma_checker.hh
View File

@@ -74,6 +74,8 @@ class PMAChecker : public SimObject
bool isUncacheable(const AddrRange &range);
bool isUncacheable(const Addr &addr, const unsigned size);
bool isUncacheable(PacketPtr pkt);
void takeOverFrom(PMAChecker *old);
};
#endif // __ARCH_RISCV_PMA_CHECKER_HH__

36
src/arch/riscv/remote_gdb.cc
View File

@@ -211,7 +211,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
// U mode CSR
r.ustatus = context->readMiscRegNoEffect(
CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS);
r.uie = context->readMiscRegNoEffect(
r.uie = context->readMiscReg(
CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE);
r.utvec = context->readMiscRegNoEffect(
CSRData.at(CSR_UTVEC).physIndex);
@@ -223,7 +223,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
CSRData.at(CSR_UCAUSE).physIndex);
r.utval = context->readMiscRegNoEffect(
CSRData.at(CSR_UTVAL).physIndex);
r.uip = context->readMiscRegNoEffect(
r.uip = context->readMiscReg(
CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP);
// S mode CSR
@@ -233,7 +233,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
CSRData.at(CSR_SEDELEG).physIndex);
r.sideleg = context->readMiscRegNoEffect(
CSRData.at(CSR_SIDELEG).physIndex);
r.sie = context->readMiscRegNoEffect(
r.sie = context->readMiscReg(
CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE);
r.stvec = context->readMiscRegNoEffect(
CSRData.at(CSR_STVEC).physIndex);
@@ -247,7 +247,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
CSRData.at(CSR_SCAUSE).physIndex);
r.stval = context->readMiscRegNoEffect(
CSRData.at(CSR_STVAL).physIndex);
r.sip = context->readMiscRegNoEffect(
r.sip = context->readMiscReg(
CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP);
r.satp = context->readMiscRegNoEffect(
CSRData.at(CSR_SATP).physIndex);
@@ -269,7 +269,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
CSRData.at(CSR_MEDELEG).physIndex);
r.mideleg = context->readMiscRegNoEffect(
CSRData.at(CSR_MIDELEG).physIndex);
r.mie = context->readMiscRegNoEffect(
r.mie = context->readMiscReg(
CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE);
r.mtvec = context->readMiscRegNoEffect(
CSRData.at(CSR_MTVEC).physIndex);
@@ -283,7 +283,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
CSRData.at(CSR_MCAUSE).physIndex);
r.mtval = context->readMiscRegNoEffect(
CSRData.at(CSR_MTVAL).physIndex);
r.mip = context->readMiscRegNoEffect(
r.mip = context->readMiscReg(
CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP);
// H mode CSR (to be implemented)
@@ -340,11 +340,11 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
newVal = (oldVal & ~mask) | (r.ustatus & mask);
context->setMiscRegNoEffect(
CSRData.at(CSR_USTATUS).physIndex, newVal);
oldVal = context->readMiscRegNoEffect(
oldVal = context->readMiscReg(
CSRData.at(CSR_UIE).physIndex);
mask = CSRMasks.at(CSR_UIE);
newVal = (oldVal & ~mask) | (r.uie & mask);
context->setMiscRegNoEffect(
context->setMiscReg(
CSRData.at(CSR_UIE).physIndex, newVal);
context->setMiscRegNoEffect(
CSRData.at(CSR_UTVEC).physIndex, r.utvec);
@@ -356,11 +356,11 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
context->setMiscRegNoEffect(
CSRData.at(CSR_UTVAL).physIndex, r.utval);
oldVal = context->readMiscRegNoEffect(
oldVal = context->readMiscReg(
CSRData.at(CSR_UIP).physIndex);
mask = CSRMasks.at(CSR_UIP);
newVal = (oldVal & ~mask) | (r.uip & mask);
context->setMiscRegNoEffect(
context->setMiscReg(
CSRData.at(CSR_UIP).physIndex, newVal);
// S mode CSR
@@ -374,11 +374,11 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
context->setMiscRegNoEffect(
CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
oldVal = context->readMiscRegNoEffect(
oldVal = context->readMiscReg(
CSRData.at(CSR_SIE).physIndex);
mask = CSRMasks.at(CSR_SIE);
newVal = (oldVal & ~mask) | (r.sie & mask);
context->setMiscRegNoEffect(
context->setMiscReg(
CSRData.at(CSR_SIE).physIndex, newVal);
context->setMiscRegNoEffect(
CSRData.at(CSR_STVEC).physIndex, r.stvec);
@@ -392,11 +392,11 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
CSRData.at(CSR_SCAUSE).physIndex, r.scause);
context->setMiscRegNoEffect(
CSRData.at(CSR_STVAL).physIndex, r.stval);
oldVal = context->readMiscRegNoEffect(
oldVal = context->readMiscReg(
CSRData.at(CSR_SIP).physIndex);
mask = CSRMasks.at(CSR_SIP);
newVal = (oldVal & ~mask) | (r.sip & mask);
context->setMiscRegNoEffect(
context->setMiscReg(
CSRData.at(CSR_SIP).physIndex, newVal);
context->setMiscRegNoEffect(
CSRData.at(CSR_SATP).physIndex, r.satp);
@@ -426,11 +426,11 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
context->setMiscRegNoEffect(
CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
oldVal = context->readMiscRegNoEffect(
oldVal = context->readMiscReg(
CSRData.at(CSR_MIE).physIndex);
mask = CSRMasks.at(CSR_MIE);
newVal = (oldVal & ~mask) | (r.mie & mask);
context->setMiscRegNoEffect(
context->setMiscReg(
CSRData.at(CSR_MIE).physIndex, newVal);
context->setMiscRegNoEffect(
CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
@@ -444,11 +444,11 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
context->setMiscRegNoEffect(
CSRData.at(CSR_MTVAL).physIndex, r.mtval);
oldVal = context->readMiscRegNoEffect(
oldVal = context->readMiscReg(
CSRData.at(CSR_MIP).physIndex);
mask = CSRMasks.at(CSR_MIP);
newVal = (oldVal & ~mask) | (r.mip & mask);
context->setMiscRegNoEffect(
context->setMiscReg(
CSRData.at(CSR_MIP).physIndex, newVal);
// H mode CSR (to be implemented)

6
src/arch/riscv/tlb.cc
View File

@@ -519,3 +519,9 @@ TLB::TlbStats::TlbStats(Stats::Group *parent)
readAccesses + writeAccesses)
{
}
Port *
TLB::getTableWalkerPort()
{
return &walker->getPort("port");
}

14
src/arch/riscv/tlb.hh
View File

@@ -92,7 +92,7 @@ class TLB : public BaseTLB
Walker *getWalker();
void takeOverFrom(BaseTLB *otlb) override {}
void takeOverFrom(BaseTLB *old) override {}
TlbEntry *insert(Addr vpn, const TlbEntry &entry);
void flushAll() override;
@@ -108,6 +108,18 @@ class TLB : public BaseTLB
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/**
* Get the table walker port. This is used for
* migrating port connections during a CPU takeOverFrom()
* call. For architectures that do not have a table walker,
* NULL is returned, hence the use of a pointer rather than a
* reference. For RISC-V this method will always return a valid
* port pointer.
*
* @return A pointer to the walker port
*/
Port *getTableWalkerPort() override;
Addr translateWithTLB(Addr vaddr, uint16_t asid, Mode mode);
Fault translateAtomic(const RequestPtr &req,