diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 9e6082a268..7d401a6c59 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -262,7 +262,7 @@ ISA::setMiscRegNoEffect(RegIndex idx, RegVal val)
         reg_width = 3;
         break;
       case misc_reg::Ftw:
-        reg_width = 8;
+        reg_width = 16;
         break;
       case misc_reg::Fsw:
       case misc_reg::Fcw:
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index a195fdf888..6589ee821d 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -397,6 +397,7 @@ X86_64Process::initState()
             tc->setMiscReg(misc_reg::Cr8, cr8);
 
             tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
+            tc->setMiscReg(misc_reg::Ftw, 0xffff);
 
             tc->setMiscReg(misc_reg::ApicBase, 0xfee00900);
 
@@ -593,6 +594,7 @@ X86_64Process::initState()
             tc->setMiscReg(misc_reg::Cr0, cr0);
 
             tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
+            tc->setMiscReg(misc_reg::Ftw, 0xffff);
 
             // Setting CR3 to the process pid so that concatinated
             // page addr with lower 12 bits of CR3 can be used in SE
@@ -727,6 +729,7 @@ I386Process::initState()
         tc->setMiscReg(misc_reg::Cr0, cr0);
 
         tc->setMiscReg(misc_reg::Mxcsr, 0x1f80);
+        tc->setMiscReg(misc_reg::Ftw, 0xffff);
     }
 }